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In the x86 architecture, the CPUID instruction (identified by a CPUID opcode) is a processor supplementary instruction (its name derived from CPU Identification) ...
CPU-Z is more comprehensive in virtually all areas compared to the tools provided in the Windows to identify various hardware components, and thus assists in identifying certain components without the need of opening the case; particularly the core revision and RAM clock rate.
CPUID model numbers are 30h-3Fh. AMD Bulldozer Family 15h – the successor to 10h/K10. Bulldozer is designed for processors in the 10 to 220 W category, implementing XOP, FMA4 and CVT16 instruction sets. Orochi was the first design which implemented it. For Bulldozer, CPUID model numbers are 00h and 01h.
The instructions below are those enabled by the BMI bit in CPUID. Intel officially considers LZCNT as part of BMI, but advertises LZCNT support using the ABM CPUID feature flag. [ 3 ] BMI1 is available in AMD's Jaguar , [ 5 ] Piledriver [ 6 ] and newer processors, and in Intel's Haswell [ 7 ] and newer processors.
The update contains information about which processors it is designed for, so that this can be checked against the result of the CPUID instruction. [1] The structure is a 48-byte header, followed by 2,000 bytes intended to be read directly by the processor to be updated: [1]
Takes as input a CPUID leaf index in EAX and, depending on leaf, a sub-index in ECX. Result is returned in EAX,EBX,ECX,EDX. [d] Instruction is serializing, and causes a mandatory #VMEXIT under virtualization. Support for CPUID can be checked by toggling bit 21 of EFLAGS (EFLAGS.ID) – if this bit can be toggled, CPUID is present. Usually 3 [e]
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With the introduction of the Pentium processor, Intel provided a pair of instructions (RDMSR and WRMSR) to access current and future "model-specific registers", as well as the CPUID instruction to determine which features are present on a particular model. Many of these registers have proven useful enough to be retained.