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The page table is a key component of virtual address translation that is necessary to access data in memory. The page table is set up by the computer's operating system, and may be read and written during the virtual address translation process by the memory management unit or by low-level system software or firmware.
For example, if a 2 32 virtual address space is mapped to 4 KiB (2 12 bytes) pages, the number of virtual pages is 2 20 = (2 32 / 2 12). However, if the page size is increased to 32 KiB (2 15 bytes), only 2 17 pages are required. A multi-level paging algorithm can decrease the memory cost of allocating a large page table for each process by ...
Most MMUs use an in-memory table of items called a page table, containing one page table entry (PTE) per virtual page, to map virtual page numbers to physical page numbers in main memory. Multi-level page tables are often used to reduce the size of the page table.
How Virtual Memory Works from HowStuffWorks.com (in fact explains only swapping concept, and not virtual memory concept) Linux swap space management (outdated, as the author admits) Guide On Optimizing Virtual Memory Speed (outdated) Virtual Memory Page Replacement Algorithms; Windows XP: How to manually change the size of the virtual memory ...
Each process has its own virtual address space. A page table maps a subset of the process virtual addresses to physical addresses. In addition, in most architectures the page table holds an "access" bit and a "dirty" bit for each page in the page table. The CPU sets the access bit when the process reads or writes memory in that page.
It is also helpful to use large pages in the host page tables to reduce the number of levels (e.g., in x86-64, using 2 MB pages removes one level in the page table). Since memory is typically allocated to virtual machines at coarse granularity, using large pages for guest-physical translation is an obvious optimization, reducing the depth of ...
First, the page table is looked up for the frame number. Second, the frame number with the page offset gives the actual address. Thus, any straightforward virtual memory scheme would have the effect of doubling the memory access time. Hence, the TLB is used to reduce the time taken to access the memory locations in the page-table method.
The page table structure used by x86-64 CPUs when operating in long mode further extends the page table hierarchy to four or more levels, extending the virtual address space, and uses additional physical address bits at all levels of the page table, extending the physical address space.