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  2. Physical Address Extension - Wikipedia

    en.wikipedia.org/wiki/Physical_Address_Extension

    On x86-64 processors in native long mode, the address translation scheme uses PAE but adds a fourth table, the 512-entry page-map level 4 table, and extends the page directory pointer table to 512 entries instead of the original 4 entries it has in protected mode. This means that 48 bits of virtual page number are translated, giving a virtual ...

  3. PSE-36 - Wikipedia

    en.wikipedia.org/wiki/PSE-36

    Compared to the Physical Address Extension (PAE) method, PSE-36 is a simpler alternative to addressing more than 4 GB of memory. It uses the Page Size Extension (PSE) mode and a modified page directory table to map 4 MB pages into a 64 GB physical address space. PSE-36's downside is that, unlike PAE, it doesn't have 4-KB page granularity above ...

  4. 3 GB barrier - Wikipedia

    en.wikipedia.org/wiki/3_GB_barrier

    Many 32-bit computers have 32 physical address bits and are thus limited to 4 GiB (2 32 words) of memory. [3] [4] x86 processors prior to the Pentium Pro have 32 or fewer physical address bits; however, most x86 processors since the Pentium Pro, which was first sold in 1995, have the Physical Address Extension (PAE) mechanism, [5]: 445 which allows addressing up to 64 GiB (2 36 words) of memory.

  5. NX bit - Wikipedia

    en.wikipedia.org/wiki/NX_bit

    It is only available with the long mode (64-bit mode) or legacy Physical Address Extension (PAE) page-table formats, but not x86's original 32-bit page table format because page table entries in that format lack the 64th bit used to disable and enable execution. Windows XP SP2 and later support Data Execution Prevention (DEP).

  6. Intel 5-level paging - Wikipedia

    en.wikipedia.org/wiki/Intel_5-level_paging

    4-level paging of the 64-bit mode. In the 4-level paging scheme (previously known as IA-32e paging), the 64-bit virtual memory address is divided into five parts. The lowest 12 bits contain the offset within the 4 KiB memory page, and the following 36 bits are evenly divided between the four 9 bit descriptors, each linking to a 64-bit page table entry in a 512-entry page table for each of the ...

  7. Page table - Wikipedia

    en.wikipedia.org/wiki/Page_table

    It was mentioned that creating a page table structure that contained mappings for every virtual page in the virtual address space could end up being wasteful. But, we can get around the excessive space concerns by putting the page table in virtual memory, and letting the virtual memory system manage the memory for the page table.

  8. Executable-space protection - Wikipedia

    en.wikipedia.org/wiki/Executable-space_protection

    The 32-bit PAE desktop kernel (linux-image-generic-pae) in Ubuntu 9.10 and later, also provides the PAE mode needed for hardware with the NX CPU feature. For systems that lack NX hardware, the 32-bit kernels now provide an approximation of the NX CPU feature via software emulation that can help block many exploits an attacker might run from ...

  9. Memory address - Wikipedia

    en.wikipedia.org/wiki/Memory_address

    On the 360/65, on S/370 models without DAT and when running with translation turned off, there are only a flat real address space and a flat absolute address space. On the 360/67, S/370 and successors through S/390, when running with translation on, addresses contain a segment number, a page number and an offset. Although early models supported ...