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Electronic design automation is used extensively to ensure that designers do not violate design rules; a process called design rule checking (DRC). DRC is a major step during physical verification signoff on the design, which also involves LVS ( layout versus schematic ) checks, XOR checks, ERC ( electrical rule check ), and antenna checks.
LVS checking software recognizes the drawn shapes of the layout that represent the electrical components of the circuit, as well as the connections between them. This netlist is compared by the "LVS" software against a similar schematic or circuit diagram's netlist. LVS checking involves following three steps:
Physical verification is a process whereby an integrated circuit layout (IC layout) design is verified via EDA software tools to ensure correct electrical and logical functionality and manufacturability. Verification involves design rule check (DRC), layout versus schematic (LVS), XOR (exclusive OR), antenna checks and electrical rule check ...
Mentor Graphics Adds Major New Design Rule Checking Product to HyperLynx Suite WILSONVILLE, Ore.--(BUSINESS WIRE)-- Mentor Graphics Corporation (NAS: MENT) today announced the release of a major ...
Laker-Calibre RealTime Integration Selected for TSMC Custom Design Reference Flow 20nm Custom Layout Flow Delivers Voltage-Dependent and Double-Patterning Signoff-Quality Design Rule Checking in ...
EDA software assists the designer in every step of the design process and every design step is accompanied by heavy test phases. Errors may be present in the high-level code already, such as for the Pentium FDIV floating-point unit bug , or it can be inserted all the way down to physical synthesis, such as a missing wire, or a timing violation .
Design rule checking (DRC) – Also sometimes known as geometric verification, this involves verifying if the design can be reliably manufactured given current photolithography limitations. In advanced process nodes, DFM rules are upgraded from optional (for better yield) to required.
Magic features real-time design rule checking, something that some costly commercial VLSI design software packages don't feature.Magic implements this by counting distance using Manhattan distance, which is much faster to compute than Euclidean distance.