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Some Xeon Phi processors support four-way hyper-threading, effectively quadrupling the number of threads. [1] Before the Coffee Lake architecture, most Xeon and all desktop and mobile Core i3 and i7 supported hyper-threading while only dual-core mobile i5's supported it.
Instructions per second (IPS) is a measure of a computer's processor speed. For complex instruction set computers (CISCs), different instructions take different amounts of time, so the value measured depends on the instruction mix; even for comparing processors in the same family the IPS measurement can be problematic.
2-way simultaneous multithreading, in-order, burst mode, 512 KB L2 cache Intel Atom Bonnell: 2008 SMT Intel Atom Silvermont: 2013 Out-of-order execution Intel Atom Goldmont: 2016 Multi-core, out-of-order execution, 3-wide superscalar pipeline, L2 cache Intel Atom Goldmont Plus: 2017 Multi-core Intel Atom Tremont: 2019
1×10 18: Fugaku 2020 Japanese supercomputer in single precision mode [15] 1.1x10 18 : Frontier 2022 U.S. supercomputer 1.88×10 18 : U.S. Summit achieves a peak throughput of this many operations per second, whilst analysing genomic data using a mixture of numerical precisions.
Itanium processor featuring an all-new microarchitecture. [26] 8 cores, decoupling in pipeline and in multithreading. 12-wide issue with partial out-of-order execution. [27] Kittson the last Itanium. It has the same microarchitecture as Poulson, but slightly higher clock speed for the top two models.
All models support DDR5-5600 or LPDDR5X-7500 in 128-bit "dual-channel" mode. CPU uses Zen4 cores (Phoenix) or a combination of Zen4 and Zen4c cores (Phoenix2). GPU uses the RDNA 3 (Navi 3) architecture. Some models include first generation Ryzen AI NPU (XDNA). All models support AVX-512 using a half-width 256-bit FPU. PCIe 4.0 support.
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