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An agree predictor is a two-level adaptive predictor with globally shared history buffer and pattern history table, and an additional local saturating counter. The outputs of the local and the global predictors are XORed with each other to give the final prediction.
The local predictor is a two-level table which records the history of individual branches. It consists of a 1,024-entry by 10-bit branch history table. A two-level table was used as the prediction accuracy is similar to that of a larger single-level table while requiring fewer bits of storage. It has a 1,024-entry branch prediction table.
The general rule for a two-level adaptive predictor with an n-bit history is that it can predict any repetitive sequence with any period if all n-bit sub-sequences are different.[8] The advantage of the two-level adaptive predictor is that it can quickly learn to predict an arbitrary repetitive pattern.
Thus, instead of using a conditional branch to select an instruction or a sequence of instructions to execute based on the predicate that controls whether the branch occurs, the instructions to be executed are associated with that predicate, so that they will be executed, or not executed, based on whether that predicate is true or false. [1]
This approach is employed in a variety of areas, including branch prediction in pipelined processors, value prediction for exploiting value locality, prefetching memory and files, and optimistic concurrency control in database systems. [1] [2] [3] Speculative multithreading is a special case of speculative execution.
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In computer architecture, a branch target predictor is the part of a processor that predicts the target, i.e., the address of the instruction that is executed next, of a taken conditional branch or unconditional branch instruction before the target of the branch instruction is computed by the execution unit of the processor.
Superscalar, branch prediction PowerPC e500: Dual 7 stage Multi-core PowerPC e600: 3-issue 7 stage Superscalar out-of-order execution, branch prediction PowerPC e5500: 2010 4-issue 7 stage Out-of-order, multi-core PowerPC e6500: 2012 Multi-core PowerPC 603: 4 5 execution units, branch prediction, no SMP PowerPC 603q: 1996 5 In-order PowerPC 604 ...