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Socket 478, also known as mPGA478 or mPGA478B, is a 478-contact CPU socket used for Intel's Pentium 4 and Celeron series CPUs. Socket 478 was launched in August 2001 in advance of the Northwood core to compete with AMD 's 462-pin Socket A and their Athlon XP processors.
Socket 478: RK80531PC017G0K: $133 Pentium 4 1.5: SL59V (C1) SL5N8 (C1) SL5TJ (D0) ... List of Intel Pentium D processors; List of Intel Celeron processors (NetBurst ...
The latest standard badge design used by Intel to promote the Celeron brand. The Celeron was a family of microprocessors from Intel targeted at the low-end consumer market. . CPUs in the Celeron brand have used designs from sixth- to eighth-generation CPU microarchitectur
Pentium 4 Willamette 1.5 GHz on Socket 423 Pentium 4 Prescott 2.4 GHz on Socket 478 Pentium 4 HT Prescott 3.0 GHz on Socket 478. At the launch of the Pentium 4, Intel stated that NetBurst-based processors were expected to scale to 10 GHz [15] after several fabrication process generations. However, the clock speed of processors using the ...
Can accept some of Socket 478 CPU with an adapter Socket 495: 2000 Intel Celeron Intel Pentium III: Notebook PGA: 495 1.27 [3] 66–133 MHz Socket 603: 2001 Intel Xeon: Server PGA: 603 1.27 [4] 100–133 MHz 400–533 MT/s Socket 478/ Socket N: 2001 Intel Pentium 4 Intel Celeron Intel Pentium 4 EE Intel Pentium 4 M: Desktop PGA: 478 1.27 [5 ...
Socket 478 Socket T: 90 nm, 130 nm 92 W – 115 W 1 /w hyperthreading 800 MHz, 1066 MHz 8 KiB ... List of Intel processors. List of Intel Atom processors;
Pages in category "Intel CPU sockets" The following 45 pages are in this category, out of 45 total. ... Socket 478; Socket 479; Socket 495; Socket 603; PAC418; PAC611 ...
Socket 8 processor package (387 pins; Dual SPGA) 5.5 million transistors; Family 6 model 1; 0.6 μm process technology. 16 KB L1 cache; 256 KB integrated L2 cache; 60 MHz system bus clock rate; Variants 150 MHz; 0.35 μm process technology, (two die, a 0.35 μm CPU with 0.6 μm L2 cache) 5.5 million transistors; 512 KB or 256 KB integrated L2 cache
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