enow.com Web Search

Search results

  1. Results from the WOW.Com Content Network
  2. Open collector - Wikipedia

    en.wikipedia.org/wiki/Open_collector

    For an NPN open emitter output, the collector is connected to the positive voltage rail, so the emitter outputs a high voltage when the transistor is on and is hi-Z when off. For a PNP open emitter output, the collector is connected to the low voltage supply, so the emitter outputs a low voltage when the transistor is on and is hi-Z when off.

  3. Wired logic connection - Wikipedia

    en.wikipedia.org/wiki/Wired_logic_connection

    See also: Diode logic § Active-high AND logic gate Open-collector buffers connected as wired AND.. The wired AND connection is a form of AND gate.When using open collector or similar outputs (which can be identified by the ⎐ symbol in schematics), wired AND only requires a pull up resistor on the shared output wire.

  4. Transistor–transistor logic - Wikipedia

    en.wikipedia.org/wiki/Transistor–transistor_logic

    A common variation omits the collector resistor of the output transistor, making an open-collector output. This allows the designer to fabricate wired logic by connecting the open-collector outputs of several logic gates together and providing a single external pull-up resistor. If any of the logic gates becomes logic low (transistor conducting ...

  5. Current-mode logic - Wikipedia

    en.wikipedia.org/wiki/Current-mode_logic

    Current mode logic (CML), or source-coupled logic (SCL), is a digital design style used both for logic gates and for board-level digital signaling of digital data.. The basic principle of CML is that current from a constant current generator is steered between two alternate paths depending on whether a logic zero or logic one is being represented.

  6. Integrated injection logic - Wikipedia

    en.wikipedia.org/wiki/Integrated_injection_logic

    The output of an inverter is at the collector. Likewise, it is either a current sink (low logic level) or a high-z floating condition (high logic level). Like direct-coupled transistor logic, there is no resistor between the output (collector) of one NPN transistor and the input (base) of the following transistor.

  7. Emitter-coupled logic - Wikipedia

    en.wikipedia.org/wiki/Emitter-coupled_logic

    The output voltages at the collector load resistors R C1 and R C3 are shifted and buffered to the inverting and non-inverting outputs by the emitter followers T4 and T5 (shaded blue). The output emitter resistors R E4 and R E5 do not exist in all versions of ECL. In some cases 50 Ω line termination resistors connected between the bases of the ...

  8. Dying To Be Free - The Huffington Post

    projects.huffingtonpost.com/dying-to-be-free...

    The high dropout rates have provoked neither an internal crisis nor a re-evaluation of programming. Stamper dismissed dropouts as “attrition by personal choice.” An addict’s failure is considered a result of not being ready for treatment, never an indication that there might be a problem with the treatment itself.

  9. 555 timer IC - Wikipedia

    en.wikipedia.org/wiki/555_timer_IC

    A 555 timer can act as an active-low SR latch (though without an inverted Q output) with two outputs: output pin is a push-pull output, discharge pin is an open-collector output (requires a pull-up resistor). For the schematic on the right, a Reset input signal connects to the RESET pin and connecting a Set input signal to the TR pin.