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Differential signalling is a method for electrically transmitting information using two complementary signals. The technique sends the same electrical signal as a differential pair of signals, each in its own conductor. The pair of conductors can be wires in a twisted-pair or ribbon cable or traces on a printed circuit board.
Low-voltage differential signaling (LVDS), also known as TIA/EIA-644, is a technical standard that specifies electrical characteristics of a differential, serial signaling standard. LVDS operates at low power and can run at very high speeds using inexpensive twisted-pair copper cables.
Current mode logic (CML), or source-coupled logic (SCL), is a digital design style used both for logic gates and for board-level digital signaling of digital data.. The basic principle of CML is that current from a constant current generator is steered between two alternate paths depending on whether a logic zero or logic one is being represented.
RS-485, also known as TIA-485(-A) or EIA-485, is a standard, originally introduced in 1983, defining the electrical characteristics of drivers and receivers for use in serial communications systems. Electrical signaling is balanced , and multipoint systems are supported.
Differential TTL is a type of binary electrical signaling based on the transistor-transistor logic (TTL) concept. It enables electronic systems to be relatively immune to noise. [ 1 ] RS-422 and RS-485 outputs can be implemented as differential TTL.
RS-422 uses a nominal 0 to 5-volt signal, while MIL-STD-188-114B uses a signal symmetric about 0 V. However, the tolerance for common-mode voltage in both specifications allows them to interoperate. Care must be taken with the termination network. RS-423 is a similar specification for unbalanced signaling.
Low-voltage positive emitter-coupled logic (LVPECL) is a power-optimized version of PECL, using a positive 3.3 V instead of 5 V supply. PECL and LVPECL are differential-signaling systems and are mainly used in high-speed and clock-distribution circuits. A common misconception is that PECL devices are slightly different from ECL devices.
On Channel 0 the C0 and C1 bits encode the Horizontal synchronization (HSync) and Vertical synchronization (VSync) signals. On the other channels they encode the CTL0 through CTL3 signals which are unused by DVI but in the case of HDMI are used as a preamble indicating the type of data about to be transferred (Video Data or Data Island), the HDCP status and so on.
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