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VEX V5 Robotics Competition (V5RC) is a robotics competition for registered middle and high school teams that utilize the VEX V5 Construction and Control System. [15] In this competition, teams design, build, and program robots to compete at tournaments.
VEX coding is also used for instructions operating on the k0-k7 mask registers that were introduced with AVX-512. The alignment requirement of SIMD memory operands is relaxed. [5] Unlike their non-VEX coded counterparts, most VEX coded vector instructions no longer require their memory operands to be aligned to the vector size.
The EVEX prefix retains fields introduced in the VEX prefix: Four bits R̅, X̅, B̅ and W from the VEX prefix, stored in inverted form. W expands the operand size to 64 bits or serves as an additional opcode, R expands reg, B expands r/m or reg, and X and B expand index and base in the SIB byte. Four bits named v̅, stored in inverted form.
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The REX prefix provides additional space for encoding 64-bit addressing modes and additional registers present in the x86-64 architecture. Bit-field W changes the operand size to 64 bits, R expands reg to 4 bits, B expands r/m (or opreg in the few opcodes that encode the register in the 3 lowest opcode bits, such as "POP reg"), and X and B expand index and base in the SIB byte.