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0.1, 0.4, 1.0, 3.4 or 5.0 ... but an output low level of 0.5 V. This method requires that all other devices on the bus have thresholds which are compatible and often ...
The HDR-DDR mode uses double data rate signalling on the SDA line with a 12.5 MHz clock to achieve a 25 Mbit/s raw data rate (20 Mbit/s effective). This requires changing the SDA line while SCK is high, a violation of the I²C protocol, but as the high-going pulse is only 40 ns long, I²C devices will ignore it and thus not notice the violation.
Examples of such systems include modern cell phones, with GND and voltages such as 1.2 V, 1.8 V, 2.4 V, 3.3 V, and PCs, with GND and voltages such as −5 V, 3.3 V, 5 V, 12 V. Power-sensitive designs often have multiple power rails at a given voltage, using them to conserve energy by switching off supplies to components that are not in active use.
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