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  2. Electronic engineering - Wikipedia

    en.wikipedia.org/wiki/Electronic_engineering

    Device technology: integrated circuit fabrication process, oxidation, diffusion, ion implantation, photolithography, n-tub, p-tub and twin-tub CMOS process. [12] [13] Analog circuits: Equivalent circuits (large and small-signal) of diodes, BJT, JFETs, and MOSFETs. Simple diode circuits, clipping, clamping, rectifier.

  3. Front end of line - Wikipedia

    en.wikipedia.org/wiki/Front_end_of_line

    Illustration of FEOL (device generation in the silicon, bottom) and BEOL (depositing metalization layers, middle part) to connect the devices. CMOS fabrication process. The front end of line (FEOL) is the first portion of IC fabrication where the individual components (transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate. [1]

  4. CMOS - Wikipedia

    en.wikipedia.org/wiki/CMOS

    CMOS inverter (a NOT logic gate). Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss ", / s iː m ɑː s /, /-ɒ s /) is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. [1]

  5. Back end of line - Wikipedia

    en.wikipedia.org/wiki/Back_end_of_line

    The BEOL process deposits metalization layers on the silicion to interconnect the individual devices generated during FEOL (bottom). CMOS fabrication process. Back end of the line or back end of line (BEOL) is a process in semiconductor device fabrication that consists of depositing metal interconnect layers onto a wafer already patterned with devices.

  6. List of semiconductor scale examples - Wikipedia

    en.wikipedia.org/wiki/List_of_semiconductor...

    TSMC began risk production of 256 Mbit SRAM memory chips using a 7 nm process in April 2017. [125] Samsung and TSMC began mass production of 7 nm devices in 2018. [126] Apple A12 and Huawei Kirin 980 mobile processors, both released in 2018, use 7 nm chips manufactured by TSMC. [127]

  7. File:CMOS fabrication process.svg - Wikipedia

    en.wikipedia.org/wiki/File:CMOS_fabrication...

    Simplified process of fabrication of a CMOS inverter: Image title: Simplified process of fabrication of a CMOS inverter on p-type substrate in semiconductor microfabrication, drawn by CMG Lee. Note: Gate, source and drain contacts are not normally in the same plane in real devices, and the diagram is not to scale.

  8. Self-aligned gate - Wikipedia

    en.wikipedia.org/wiki/Self-aligned_gate

    Key to the advance was the discovery that heavily doped poly-silicon was conductive enough to replace aluminum. This meant the gate layer could be created at any stage in the multi-step fabrication process. [1]: p.1 (see Fig. 1.1) In the self-aligned process, the key gate-insulating layer is formed near the beginning of the process.

  9. Wafer fabrication - Wikipedia

    en.wikipedia.org/wiki/Wafer_fabrication

    Wafer fabrication is a procedure composed of many repeated sequential processes to produce complete electrical or photonic circuits on semiconductor wafers in a semiconductor device fabrication process. Examples include production of radio frequency amplifiers, LEDs, optical computer components, and microprocessors for computers. Wafer ...