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Socket SP3 is a zero insertion force land grid array CPU socket designed by AMD supporting its Zen-, Zen 2- and Zen 3-based Epyc server processors, [1] [2] launched on June 20, 2017. [3] Because the socket is physically the same size as socket TR4 and socket sTRX4 , users can use CPU coolers not only designed for SP3, but also coolers designed ...
Socket 1 Socket 2 Socket 3 0.6 – 1-micron 1 25 MHz – 50 MHz 8 KiB – 16 KiB N/A N/A Intel Pentium: N/A P5 P54C P54CTB P54CS 1993–1999 65 MHz – 250 MHz Socket 2 Socket 3 Socket 4 Socket 5 Socket 7: 350 nm – 800 nm Unknown 1 50 MHz – 66 MHz 16 KiB N/A N/A Intel Pentium MMX: N/A P55C Tillamook 1996–1999 120 MHz – 300 MHz Socket 7
Socket 939: Troy 200 Socket 940: Athens 800 Denmark 100 2 1600–3200 1000 HT Socket 939: AMD64, NX Bit: Italy 200 1600–3200 Socket 940: AMD64, NX Bit, ccNUMA: Egypt 800 1600–3200 Santa Ana 1200 1800–3200 Socket AM2: DDR2: AMD64, NX Bit: Santa Rosa 2200 1800–3200 Socket F: 8200 2000–3000 130 Athlon 64 FX: Sledgehammer FX-51, FX-53 1 ...
The Epyc server line of chips based on Zen 3 is named Milan and is the final generation of chips using the SP3 socket. [6] Epyc Milan was released on March 15, 2021. [65] Common features: SP3 socket; Zen 3 microarchitecture; TSMC 7 nm process for the compute and cache dies, GloFo 14 nm process for the I/O die
It is possible to use Socket 7 processors in a Socket 5. An adapter is required, or if one is careful, a socket 7 can be pulled off its pins and put onto a socket 5 board, allowing the use of socket 7 processors. Socket 8: 1995 Intel Pentium Pro: PGA: 387 ? 60–66 MHz Slot 1: 1997 Intel Pentium II Intel Pentium III: Desktop Slot: 242 ? 66 ...
Socket 8 processor package (387 pins; Dual SPGA) 5.5 million transistors; Family 6 model 1; 0.6 μm process technology. 16 KB L1 cache; 256 KB integrated L2 cache; 60 MHz system bus clock rate; Variants 150 MHz; 0.35 μm process technology, (two die, a 0.35 μm CPU with 0.6 μm L2 cache) 5.5 million transistors; 512 KB or 256 KB integrated L2 cache
Socket: AM4. All the CPUs support DDR4-2666 in dual-channel mode. All the CPUs support 24 PCIe 3.0 lanes. 4 of the lanes are reserved as link to the chipset. No integrated graphics. L1 cache: 96 KB (32 KB data + 64 KB instruction) per core. L2 cache: 512 KB per core. Node/fabrication process: GlobalFoundries 14 LP.
Socket sTRX4, also known as Socket SP3r3, [1] is a land grid array (LGA) CPU socket designed by AMD supporting its Zen 2-based third-generation Ryzen Threadripper desktop processors, [2] launched on November 25, 2019 for the high-end desktop and workstation platforms.