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The AMD Jaguar Family 16h is a low-power microarchitecture designed by AMD. It is used in APUs succeeding the Bobcat Family microarchitecture in 2013 and being succeeded by AMD's Puma architecture in 2014. It is two-way superscalar and capable of out-of-order execution.
AMD Family 10h (K10) – based on the K8 microarchitecture. Shared Level 3 Cache, 128-bit floating point units, AMD-V Nested Paging virtualization, and HyperTransport 3.0 are introduced. Barcelona was the first design which implemented it. AMD Family 11h – combined elements of K8 and K10 designs for Turion X2 Ultra / Puma mobile platform.
The Puma cores use the same microarchitecture as Jaguar, and inherits the design: Out-of-order execution and Speculative execution, up to 4 CPU cores; Two-way integer execution; Two-way 128-bit wide floating-point and packed integer execution; Integer hardware divider; Puma does not feature clustered multi-thread (CMT), meaning that there are ...
The AMD Bobcat Family 14h is a microarchitecture created by AMD for its AMD APUs, aimed at a low-power/low-cost market. [ 1 ] It was revealed during a speech from AMD executive vice-president Henri Richard in Computex 2007 and was put into production Q1 2011. [ 2 ]
Zen+ is the name for a computer processor microarchitecture by AMD.It is the successor to the first gen Zen microarchitecture, [3] and was first released in April 2018, [4] powering the second generation of Ryzen processors, known as Ryzen 2000 for mainstream desktop systems, Threadripper 2000 for high-end desktop setups and Ryzen 3000G (instead of 2000G) for accelerated processing units (APUs).
AMD Steamroller Family 15h is a microarchitecture developed by AMD for AMD APUs, which succeeded Piledriver in the beginning of 2014 as the third-generation Bulldozer-based microarchitecture. [2] Steamroller APUs continue to use two-core modules as their predecessors, while aiming at achieving greater levels of parallelism.
Heterogeneous System Architecture (HSA) is a cross-vendor set of specifications that allow for the integration of central processing units and graphics processors on the same bus, with shared memory and tasks. [1]
Each CPU can access the main memory of another processor, transparent to the programmer. The Opteron approach to multi-processing is not the same as standard symmetric multiprocessing; instead of having one bank of memory for all CPUs, each CPU has its own memory. Thus the Opteron is a Non-Uniform Memory Access (NUMA) architecture. The Opteron ...