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In computer architecture, a control bus is part of the system bus and is used by CPUs for communicating with other devices within the computer. While the address bus carries the information about the device with which the CPU is communicating and the data bus carries the actual data being processed, the control bus carries commands from the CPU and returns status signals from the devices.
A system bus is a single computer bus that connects the major components of a computer system, combining the functions of a data bus to carry information, an address bus to determine where it should be sent or read from, and a control bus to determine its operation. The technique was developed to reduce costs and improve modularity, and ...
The simplest system bus has completely separate input data lines, output data lines, and address lines. To reduce cost, most microcomputers have a bidirectional data bus, re-using the same wires for input and output at different times. [20] Some processors use a dedicated wire for each bit of the address bus, data bus, and the control bus.
The Bus controller commands the RT that is the destination of the data (e.g. RT2) to receive the data at a specified (receive) data sub-address and then commands RT1 to transmit from the transmit sub-address specified in the command.
The memory controller manages access to memory using the memory bus or a system bus, or through separate control, address, and data buses, to execute the program's commands. The bus managed by the memory controller consists of multiple parallel lines, each representing a binary digit (bit).
An initiator has also to provide the data related to the specified address(es) on the Write data channel: the data on WDATA; the "strobe" bits on WSTRB (if present), which conditionally mark the individual WDATA bytes as "valid" or "invalid" Like in the read path, on the last data word, WLAST has to be asserted by the initiator.
The bus is completely asynchronous, allowing a mixture of fast and slow devices. It allows the overlapping of arbitration (selection of the next bus master) while the current bus master is still performing data transfers. The 18 address lines allow the addressing of a maximum of 256 KB.
The bus signal definitions closely follow those of an 8080 microprocessor system, since the Intel 8080 microprocessor was the first microprocessor hosted on the S-100 bus. The 100 lines of the S-100 bus can be grouped into four types: 1) Power, 2) Data, 3) Address, and 4) Clock and control. [1]