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Previous HDMI versions use three data channels (each operating at up to 6.0 Gbit/s in HDMI 2.0, or up to 3.4 Gbit/s in HDMI 1.4), with an additional channel for the TMDS clock signal, which runs at a fraction of the data channel speed (one tenth the speed, or up to 340 MHz, for signaling rates up to 3.4 Gbit/s; one fortieth the speed, or up to ...
Additional clock precision in 0.25 MHz increments (to be subtracted from byte 9 maximum pixel clock rate) Bits 1–0: Maximum active pixels per line, 2-bit msb 13: Maximum active pixels per line, 8-bit lsb (no limit if 0) 14: Aspect ratio bitmap Bit 7: 4∶3 Bit 6: 16∶9 Bit 5: 16∶10 Bit 4: 5∶4 Bit 3: 15∶9 Bits 2–0: 000 = reserved 15 ...
In revision 1.2, released in 2013, a new "Reduced Blanking Timing Version 2" mode was added which further reduces the horizontal blanking interval from 160 to 80 pixels, increases pixel clock precision from ±0.25 MHz to ±0.001 MHz, and adds the option for a 1000/1001 modifier for ATSC/NTSC video-optimized timing modes (e.g. 59.94 Hz instead ...
2 = HDMI VIC code 2: 1–248: Number of payload bytes 0x24 Type IX formula-based timings ... Pixel clock, 10 kHz steps (0.01–167,772.16 MPix/s) 3 Timing options
In each TMDS clock period there is a 10-bit symbol per TMDS data pair representing 8-bits of pixel color. In single link mode each set of three 10-bit symbols represents one 24-bit pixel, while in dual link mode each set of six 10-bit symbols either represents two 24-bit pixels or one pixel of up to 48-bit color depth .
The normal (24 bit) mode operates at 2.25 Gbit/s, and multiplexes the same three channel, 24 bit color signal as HDMI, at a pixel clock rate of up to 75 MHz, sufficient for 1080i and 720p at 60 Hz. One period of the MHL clock equals one period of the pixel clock, and each period of the MHL clock transmits three 10-bit TMDS characters (i.e., a ...
Four times the resolution of 1080p. Requires a dual-link DVI, category 2 (high-speed) HDMI, DisplayPort or a single Thunderbolt link, and a reduced scan rate (up to 30 Hz); a DisplayPort 1.2 connection can support this resolution at 60 Hz, or 30 Hz in stereoscopic 3D. 3840×2160 (8,294k) 3840 2160 8,294,400 16:9 24 bpp DCI 4K
The original FPD-Link designed for 18-bit RGB video has 3 parallel data pairs and a clock pair, so this is a parallel communication scheme. However, each of the 3 pairs transfers 7 serialized bits during each clock cycle. So the FPD-Link parallel pairs are carrying serialized data, but use a parallel clock to recover and synchronize the data.