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  2. LGA 1155 - Wikipedia

    en.wikipedia.org/wiki/LGA_1155

    View of the socket LGA 1155 on an Intel Core i7 Sandy Bridge 2600K model CPU Celeron G530 "Sandy Bridge" installed on a Socket 1155. LGA 1155, also called Socket H2, is a zero insertion force flip-chip land grid array (LGA) CPU socket designed by Intel for their CPUs based on the Sandy Bridge (second generation core) and Ivy Bridge (third generation) microarchitectures.

  3. Ivy Bridge (microarchitecture) - Wikipedia

    en.wikipedia.org/wiki/Ivy_Bridge_(microarchitecture)

    Ivy Bridge processors are backward compatible with the Sandy Bridge platform, ... LGA 1155: DMI 2.0 PCIe 3.0: Up to dual channel DDR3-1600 1280v2: 3.6 GHz 4.0 GHz

  4. List of Intel Xeon processors (Ivy Bridge-based) - Wikipedia

    en.wikipedia.org/wiki/List_of_Intel_Xeon...

    All models support uni-processor configurations only. ... LGA 1155 DMI 2.0 May 14, 2012 CM8063701213802; OEM "Ivy Bridge-EN" (22 nm) Entry.

  5. List of Intel Xeon processors (Sandy Bridge-based) - Wikipedia

    en.wikipedia.org/wiki/List_of_Intel_Xeon...

    All models support uni-processor configurations only. ... LGA 1155 DMI 2.0 April 3, 2011 CM8062301149700; OEM "Sandy Bridge-EN" (32 nm) Entry.

  6. List of Intel Celeron processors - Wikipedia

    en.wikipedia.org/wiki/List_of_Intel_Celeron...

    LGA 1700 DMI 4.0 ×8 January 2022 SRL6Q (H0) CM8071504653807 $44 Low power: Celeron G6900T: 2 (2) 2.8 GHz — 2 × 1.25 MB 4 MB UHD 710 300–1300 MHz 35 W — LGA 1700 DMI 4.0 ×8 January 2022 SRL68 (H0) CM8071504651904 $42 Low power, embedded: Celeron G6900TE: 2 (2) 2.4 GHz — 2 × 1.25 MB 4 MB UHD 710 300–1300 MHz 35 W — LGA 1700 DMI 4. ...

  7. List of Intel Core processors - Wikipedia

    en.wikipedia.org/wiki/List_of_Intel_Core_processors

    Socket: LGA 1155. All the CPUs support dual-channel DDR3 RAM, at up to 1600 MT/s speed. All CPU models provide 16 lanes of PCIe. i5 and up models support it at PCIe 3.0 speeds while i3 models support it at PCIe 2.0 speeds. All CPUs feature a DMI 2.0 bus to the chipset . L1 cache: 64 KB (32 KB data + 32 KB instructions) per core.

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