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The input to a fault diagnostic is a tester datalog showing the failure characteristics of the device. The diagnostic algorithm uses an internal simulation of a fault model of the electrical circuit in order to compare the failure characteristics of the actual device with a set of simulated failure characteristics.
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In semiconductor devices, parasitic structures, irrelevant for normal operation, become important in the context of failures; they can be both a source and protection against failure. Applications such as aerospace systems, life support systems, telecommunications, railway signals, and computers use great numbers of individual electronic ...
A stress test (sometimes called a torture test) of hardware is a form of deliberately intense and thorough testing used to determine the stability of a given system or entity. It involves testing beyond normal operational capacity , often to a breaking point, in order to observe the results.
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ATPG (acronym for both automatic test pattern generation and automatic test pattern generator) is an electronic design automation method or technology used to find an input (or test) sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects.
Wafer testing is a step performed during semiconductor device fabrication after back end of line (BEOL) and before IC packaging.. Two types of testing are typically done. Very basic wafer parametric tests (WPT) are performed at a few locations on each wafer to ensure the wafer fabrication process has been carried out successfully.
The best way to achieve high confidence is to leverage the pre-silicon verification work — which can comprise as much as 30% of the overall cost of the implementation — and use that knowledge in the post-silicon system. Today, much of this work is done manually, which partially explains the high costs associated with system validation.