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  2. Itanium - Wikipedia

    en.wikipedia.org/wiki/Itanium

    Itanium never sold well outside enterprise servers and high-performance computing systems, and the architecture was ultimately supplanted by competitor AMD's x86-64 (also called AMD64) architecture. x86-64 is a compatible extension to the 32-bit x86 architecture, implemented by, for example, Intel's own Xeon line and AMD's Opteron line.

  3. IA-64 - Wikipedia

    en.wikipedia.org/wiki/IA-64

    IA-64 (Intel Itanium architecture) is the instruction set architecture (ISA) of the discontinued Itanium family of 64-bit Intel microprocessors. The basic ISA specification originated at Hewlett-Packard (HP), and was subsequently implemented by Intel in collaboration with HP. The first Itanium processor, codenamed Merced, was released in 2001.

  4. List of Intel Itanium processors - Wikipedia

    en.wikipedia.org/wiki/List_of_Intel_Itanium...

    Itanium 2 uses socket PAC611 with a 128 bit wide FSB.The 90 nm CPUs (9000 and 9100 series) bring dual-core chips and an updated microarchitecture adding multithreading and splitting the L2 cache into a 256 KB data cache and 1 MB instruction cache per core (the pre-9000 series L2 cache being a 256 KB common cache).

  5. List of Intel CPU microarchitectures - Wikipedia

    en.wikipedia.org/wiki/List_of_Intel_CPU_micro...

    Itanium processor featuring an all-new microarchitecture. [26] 8 cores, decoupling in pipeline and in multithreading. 12-wide issue with partial out-of-order execution. [27] Kittson the last Itanium. It has the same microarchitecture as Poulson, but slightly higher clock speed for the top two models.

  6. HPE Integrity Servers - Wikipedia

    en.wikipedia.org/wiki/HPE_Integrity_Servers

    The 10U rx7640 is based on the SX2000 chipset which supports both PA-RISC and Itanium 2 CPUs. Maximum of 2 cell boards; 4 CPU sockets per cell board; 16 DIMM slots per cell board; Maximum of 4 SCSI disks and 2 tape and/or CD/DVD-ROM internally (half to each cell board) 7 hot-pluggable I/O slots per cell board plus 1 core I/O slot per cell board ...

  7. Explicitly parallel instruction computing - Wikipedia

    en.wikipedia.org/wiki/Explicitly_parallel...

    It was the basis for Intel and HP development of the Intel Itanium architecture, [3] and HP later asserted that "EPIC" was merely an old term for the Itanium architecture. [4] EPIC permits microprocessors to execute software instructions in parallel by using the compiler, rather than complex on-die circuitry, to control parallel instruction ...

  8. List of Intel processors - Wikipedia

    en.wikipedia.org/wiki/List_of_Intel_processors

    Iris Plus: 300: 1100 15 Ice Lake: BGA 1526: ... Used segment registers to access more than 64 KB of data at ... Pentium 4 (not 4EE, 4E, 4F), Itanium, P4-based Xeon ...

  9. OpenVMS - Wikipedia

    en.wikipedia.org/wiki/OpenVMS

    In 2001, prior to its acquisition by Hewlett-Packard, Compaq announced the port of OpenVMS to the Intel Itanium architecture. [64] The Itanium port was the result of Compaq's decision to discontinue future development of the Alpha architecture in favour of adopting the then-new Itanium architecture. [65]