Search results
Results from the WOW.Com Content Network
The predecessor of the 80386 was the Intel 80286, a 16-bit processor with a segment-based memory management and protection system. The 80386 added a three-stage instruction pipeline which it brought up to total of 6-stage instruction pipeline, extended the architecture from 16-bits to 32-bits, and added an on-chip memory management unit. [21]
Since the base is set to 0 in all cases and the limit 4 GiB, the segmentation unit does not affect the addresses the program issues before they arrive at the paging unit. (This, of course, refers to 80386 and later processors, as the earlier x86 processors do not have a paging unit.) Current Linux also uses GS to point to thread-local storage.
The primary defining characteristic of IA-32 is the availability of 32-bit general-purpose processor registers (for example, EAX and EBX), 32-bit integer arithmetic and logical operations, 32-bit offsets within a segment in protected mode, and the translation of segmented addresses to 32-bit linear addresses.
The 80386 had an optional floating-point coprocessor, the 80387; it had eight 80-bit wide registers: st(0) to st(7), [33] like the 8087 and 80287. The 80386 could also use an 80287 coprocessor. [34] With the 80486 and all subsequent x86 models, the floating-point processing unit (FPU) is integrated on-chip.
In a system using segmentation, computer memory addresses consist of a segment id and an offset within the segment. [3] A hardware memory management unit (MMU) is responsible for translating the segment and offset into a physical address, and for performing checks to make sure the translation can be done and that the reference to that segment and offset is permitted.
In computing, protected mode, also called protected virtual address mode, [1] is an operational mode of x86-compatible central processing units (CPUs). It allows system software to use features such as segmentation, virtual memory, paging and safe multi-tasking designed to increase an operating system's control over application software.
The paging mechanism uses an on-chip page table with 16Kbyte pages and no access rights checking. [35] V33, V53 [32] RETXA imm8: 0F F0 ib: Return from Extended Address Mode. Jump to an address picked from the IVT using the imm8 argument. Disables paging after reading the IVT but before executing the jump. MOVSPA: 0F 25
Though the 80386 was a 32 bit CPU, it was limited to a 16-bit I/O bus in the case of the Intel Inboard 386/AT and an 8-bit I/O bus in the case of the Intel Inboard 386/PC. Both boards retained 32-bit data and address buses, however.