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A six-transistor (6T) CMOS SRAM cell. WL: word line. BL: bit line. A typical SRAM cell is made up of six MOSFETs, and is often called a 6T SRAM cell. Each bit in the cell is stored on four transistors (M1, M2, M3, M4) that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1.
English: Circuit diagram of an SRAM cell, built with six MOSFETs. The bulk connection of all transistors is to ground, but is not shown from simplicity. The bulk connection of all transistors is to ground, but is not shown from simplicity.
This led to his development of a single-transistor DRAM memory cell. [18] In 1967, Dennard filed a patent under IBM for a single-transistor DRAM memory cell, based on MOS technology. [ 23 ] The first commercial DRAM IC chip was the Intel 1103 , which was manufactured on an 8 μm MOS process with a capacity of 1 kbit , and was released in 1970.
This led to his development of a single-transistor DRAM memory cell. [20] In 1967, Dennard filed a patent for a single-transistor DRAM memory cell, based on MOS technology. [21] The first commercial bipolar 64-bit SRAM was released by Intel in 1969 with the 3101 Schottky TTL.
SRAM became an alternative to magnetic-core memory, but required six MOS transistors for each bit of data. [21] Commercial use of SRAM began in 1965, when IBM introduced their SP95 SRAM chip for the System/360 Model 95. [9] Toshiba introduced bipolar DRAM memory cells for its Toscal BC-1411 electronic calculator in 1965.
The necessity of introducing double patterning and hyper-NA tools to reduce memory cell area offset some of the cost advantages of moving to this node from the 45 nm node. [12] TSMC similarly used double patterning combined with immersion lithography to produce a "32 nm" node 0.183 μm 2 six-transistor SRAM cell in 2005. [13]
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On August 18, 2008, AMD, Freescale, IBM, STMicroelectronics, Toshiba, and the College of Nanoscale Science and Engineering (CNSE) announced that they jointly developed and manufactured a 22 nm SRAM cell, built on a traditional six-transistor design on a 300 mm wafer, which had a memory cell size of just 0.1 μm 2. [7]