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For an NPN open emitter output, the collector is connected to the positive voltage rail, so the emitter outputs a high voltage when the transistor is on and is hi-Z when off. For a PNP open emitter output, the collector is connected to the low voltage supply, so the emitter outputs a low voltage when the transistor is on and is hi-Z when off.
The open collector input/output is a popular alternative to three-state logic. For example, the I²C bus protocol (a bi-directional communication bus protocol often used between devices) specifies the use of pull-up resistors on the two communication lines. When devices are inactive, they "release" the communication lines and tri-state their ...
See also: Diode logic § Active-high AND logic gate Open-collector buffers connected as wired AND.. The wired AND connection is a form of AND gate.When using open collector or similar outputs (which can be identified by the ⎐ symbol in schematics), wired AND only requires a pull up resistor on the shared output wire.
A common variation omits the collector resistor of the output transistor, making an open-collector output. This allows the designer to fabricate wired logic by connecting the open-collector outputs of several logic gates together and providing a single external pull-up resistor. If any of the logic gates becomes logic low (transistor conducting ...
Schematic of a multi-transistor RTL NOR gate, as used in the Apollo Guidance Computer integrated circuits. [4] Photograph of the dual 3-input NOR gate chip used to build the Apollo Guidance Computer. Connections (clockwise from top center) ground, inputs (3), output, power (V cc), output, inputs (3). The six transistors (two groups of three ...
The high power consumption of ECL meant that it has been used mainly when high speed is a vital requirement. Older high-end mainframe computers, such as the Enterprise System/9000 members of IBM's ESA/390 computer family, used ECL, [26] as did the Cray-1; [27] and first-generation Amdahl mainframes. (Current IBM mainframes use CMOS. [28])
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As an example, here is a NOR gate implemented in schematic NMOS. If either input A or input B is high (logic 1, = True), the respective MOS transistor acts as a very low resistance between the output and the negative supply, forcing the output to be low (logic 0, = False).