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When cascading flip-flops which share the same clock (as in a shift register), it is important to ensure that the t CO of a preceding flip-flop is longer than the hold time (t h) of the following flip-flop, so data present at the input of the succeeding flip-flop is properly "shifted in" following the active edge of the clock.
Here, the contamination delay is the amount of time needed for a change in the flip-flop clock input to result in the initial change at the flip-flop output (Q). If there is insufficient delay from the output of the first flip-flop to the input of the second, the input may change before the hold time has passed. Because the second flip-flop is ...
In a synchronous circuit, two registers, or flip-flops, are said to be "sequentially adjacent" if a logic path connects them. Given two sequentially adjacent registers R i and R j with clock arrival times at the source and destination register clock pins equal to T C i and T C j respectively, clock skew can be defined as: T skew i, j = T C i ...
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Synchronizers may take the form of a cascade of D flip-flops (e.g. the shift register in Figure 3). [7] Although each flip-flop stage adds an additional clock cycle of latency to the input data stream, each stage provides an opportunity to resolve metastability. Such synchronizers can be engineered to reduce metastability to a tolerable rate.
A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is fixed relative to the phase of an input signal. Keeping the input and output phase in lockstep also implies keeping the input and output frequencies the same, thus a phase-locked loop can also track an input frequency.
An asynchronous (ripple) counter is a "chain" of toggle (T) flip-flops in which the least-significant flip-flop (bit 0) is clocked by an external signal (the counter input clock), and all other flip-flops are clocked by the output of the nearest, less significant flip-flop (e.g., bit 0 clocks the bit 1 flip-flop, bit 1 clocks the bit 2 flip ...
The straight ring counter has the logical structure shown here: Instead of the reset line setting up the initial one-hot pattern, the straight ring is sometimes made self-initializing by the use of a distributed feedback gate across all of the outputs except that last, so that a 1 is presented at the input when there is no 1 in any stage but the last.