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The Advanced eXtensible Interface (AXI) is an on-chip communication bus protocol and is part of the Advanced Microcontroller Bus Architecture specification (AMBA). [ 1 ] [ 2 ] AXI had been introduced in 2003 with the AMBA3 specification.
In its second version, AMBA 2 in 1999, Arm added AMBA High-performance Bus (AHB) that is a single clock-edge protocol. In 2003, Arm introduced the third generation, AMBA 3, including Advanced eXtensible Interface (AXI) to reach even higher performance interconnect and the Advanced Trace Bus (ATB) as part of the CoreSight on-chip debug and trace ...
Master and Slave Wishbone's interfaces. The Wishbone Bus is an open source hardware computer bus intended to let the parts of an integrated circuit communicate with each other.
The Open Core Protocol (OCP) is one of several FPGA processor interconnects used to connect soft FPGA peripherals to FPGA CPUs—both soft microprocessor and hard-macro processor. Other such interconnects include Advanced eXtensible Interface (AXI), Avalon, [1] and the Wishbone bus.
The ccTalk multidrop bus protocol uses an 8 bit TTL-level asynchronous serial protocol.It uses address randomization to allow multiple similar devices on the bus (after randomisation the devices can be distinguished by their serial number). ccTalk was developed by CoinControls, but is used by multiple vendors.
The Intel QuickPath Interconnect (QPI) [1] [2] is a scalable processor interconnect developed by Intel which replaced the front-side bus (FSB) in Xeon, Itanium, and certain desktop platforms starting in 2008. It increased the scalability and available bandwidth.
The Scalable Coherent Interface or Scalable Coherent Interconnect (SCI), is a high-speed interconnect standard for shared memory multiprocessing and message passing.The goal was to scale well, provide system-wide memory coherence and a simple interface; i.e. a standard to replace existing buses in multiprocessor systems with one with no inherent scalability and performance limitations.
The Runway bus is a front-side bus developed by Hewlett-Packard for use by its PA-RISC microprocessor family. The Runway bus is a 64-bit wide, split transaction, time multiplexed address and data bus running at 120 MHz.