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  2. Semiconductor device fabrication - Wikipedia

    en.wikipedia.org/wiki/Semiconductor_device...

    The fabrication process is performed in highly specialized semiconductor fabrication plants, also called foundries or "fabs", [1] with the central part being the "clean room". In more advanced semiconductor devices, such as modern 14 / 10 / 7 nm nodes, fabrication can take up to 15 weeks, with 11–13 weeks being the industry average. [ 2 ]

  3. Self-aligned gate - Wikipedia

    en.wikipedia.org/wiki/Self-aligned_gate

    In semiconductor electronics fabrication technology, a self-aligned gate is a transistor manufacturing approach whereby the gate electrode of a MOSFET (metal–oxide–semiconductor field-effect transistor) is used as a mask for the doping of the source and drain regions. This technique ensures that the gate is naturally and precisely aligned ...

  4. MOSFET - Wikipedia

    en.wikipedia.org/wiki/MOSFET

    In the MOSFET IC fabrication process, it is preferable to deposit the gate material prior to certain high-temperature steps in order to make better-performing transistors. Such high temperature steps would melt some metals, limiting the types of metal that can be used in a metal-gate-based process.

  5. 22 nm process - Wikipedia

    en.wikipedia.org/wiki/22_nm_process

    The "22 nm" node is the process step following 32 nm in CMOS MOSFET semiconductor device fabrication. The typical half-pitch (i.e., half the distance between identical features in an array) for a memory cell using the process is around 22 nm. [citation needed] It was first demonstrated by semiconductor companies for use in RAM in 2008.

  6. Front end of line - Wikipedia

    en.wikipedia.org/wiki/Front_end_of_line

    Illustration of FEOL (device generation in the silicon, bottom) and BEOL (depositing metalization layers, middle part) to connect the devices. CMOS fabrication process. The front end of line (FEOL) is the first portion of IC fabrication where the individual components (transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate. [1]

  7. 5 nm process - Wikipedia

    en.wikipedia.org/wiki/5_nm_process

    In 2002, an IBM research team including Bruce Doris, Omer Dokumaci, Meikei Ieong and Anda Mocuta fabricated a 6-nanometre silicon-on-insulator (SOI) MOSFET. [8] [9] In 2003, a Japanese research team at NEC, led by Hitoshi Wakabayashi and Shigeharu Yamagami, fabricated the first 5 nm MOSFET. [10] [11] In 2015, IMEC and Cadence fabricated 5 nm ...

  8. 3 nm process - Wikipedia

    en.wikipedia.org/wiki/3_nm_process

    In 2003, a research team at NEC fabricated the first MOSFETs with a channel length of 3 nm, using the PMOS and NMOS processes. [20] [21] In 2006, a team from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center, developed a 3 nm width multi-gate MOSFET, the world's smallest nanoelectronic device, based on gate-all-around technology.

  9. 7 nm process - Wikipedia

    en.wikipedia.org/wiki/7_nm_process

    In semiconductor manufacturing, the "7 nm" process is a term for the MOSFET technology node following the "10 nm" node, defined by the International Roadmap for Devices and Systems (IRDS), which was preceded by the International Technology Roadmap for Semiconductors (ITRS).