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Nehalem / n ə ˈ h eɪ l əm / [1] is the codename for Intel's 45 nm microarchitecture released in November 2008. [2] It was used in the first generation of the Intel Core i5 and i7 processors, and succeeds the older Core microarchitecture used on Core 2 processors. [3]
The following is a partial list of Intel CPU microarchitectures. The list is incomplete, additional details can be found in Intel's tick–tock model, process–architecture–optimization model and Template:Intel processor roadmap.
Based on Nehalem microarchitecture; All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, Demand-Based Switching (Intel's Server EIST), Intel 64, XD bit (an NX bit implementation), Intel VT-x, Intel EPT, Intel VT-d, Intel VT-c, [6] Intel x8 SDDC [2] [7]
Intel X58 Express desktop chipset, and also the name of a gaming platform combining this chipset with Core i7 and Core i7 Extreme Edition (Nehalem and Westmere) CPUs. Also the 5500 and 5520 chipsets, used in two-socket servers with the Xeon 5500 and 5600 ( Gainestown and Westmere -EP) CPUs.
Toggle Nehalem-based subsection. 5.1 Xeon 3000 series. 5.2 Xeon 5000 series. ... The following is a list of Intel Xeon microprocessors, by generation. Intel Xeon E5 ...
Westmere (formerly Nehalem-C) is the code name given to the 32 nm die shrink of Nehalem. While sharing the same CPU sockets , Westmere included Intel HD Graphics , while Nehalem did not. The first Westmere -based processors were launched on January 7, 2010, by Intel Corporation.
Bloomfield (or Nehalem-E) is the codename for the successor to the Xeon 3300 series, is based on the Nehalem microarchitecture and uses the same 45 nm manufacturing methods as Intel's Penryn. The first processor released with the Nehalem architecture is the high-end desktop Core i7 , which was released in November 2008.
Intel's implementation of SLAT, known as Extended Page Table (EPT), was introduced in the Nehalem microarchitecture found in certain Core i7, Core i5, and Core i3 processors. ARM's virtualization extensions support SLAT, known as Stage-2 page-tables provided by a Stage-2 MMU. The guest uses the Stage-1 MMU.