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Intel 5-level paging, referred to simply as 5-level paging in Intel documents, is a processor extension for the x86-64 line of processors. [ 1 ] : 11 It extends the size of virtual addresses from 48 bits to 57 bits by adding an additional level to x86-64's multilevel page tables , increasing the addressable virtual memory from 256 TiB to 128 PiB .
For some processors, a mode can be enabled with a fifth table, the 512-entry page-map level 5 table; this means that 57 bits of virtual page number are translated, giving a virtual address space of up to 128 PB. [10]: 141–153 In the page table entries, in the original specification, 40 bits of physical page number are implemented.
In computing, a page fault is an exception that the memory management unit (MMU) raises when a process accesses a memory page without proper preparations. Accessing the page requires a mapping to be added to the process's virtual address space. Furthermore, the actual page contents may need to be loaded from a back-up, e.g. a disk.
A control register is a processor register that changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode , paging control, and coprocessor control.
The page-directory entry with PS set to 0 behaves as without PSE. If newer PSE-36 capability is available on the CPU, as checked using the CPUID instruction, then 4 more bits, in addition to normal 10 bits, are used inside a page-directory entry pointing to a large page. This allows a large page to be located in 36-bit address space.
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