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The Intel QuickPath Interconnect (QPI) [1] [2] is a scalable processor interconnect developed by Intel which replaced the front-side bus (FSB) in Xeon, Itanium, and certain desktop platforms starting in 2008. It increased the scalability and available bandwidth. Prior to the name's announcement, Intel referred to it as Common System Interface ...
The Intel X58 (codenamed Tylersburg) is an Intel chip designed to connect Intel processors with Intel QuickPath Interconnect (QPI) interface to peripheral devices. Supported processors implement the Nehalem microarchitecture and therefore have an integrated memory controller (IMC), so the X58 does not have a memory interface.
More modern designs use point-to-point and serial connections like AMD's HyperTransport and Intel's DMI 2.0 or QuickPath Interconnect (QPI). These implementations remove the traditional northbridge in favor of a direct link from the CPU to the system memory, high-speed peripherals, and the Platform Controller Hub, southbridge or I/O controller.
UPI is a low-latency coherent interconnect for scalable multiprocessor systems with a shared address space. It uses a directory-based home snoop coherency protocol with a transfer speed of up to 10.4 GT/s. Supporting processors typically have two or three UPI links.
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Xeon processor-based systems are among the top 20 fastest systems by memory bandwidth as measured by the STREAM benchmark. [52] An Intel Xeon virtual SMP system using ScaleMP's Versatile SMP (vSMP) architecture with 128 cores and 1 TiB RAM. [53] This system aggregates 16 Stoakley platform (Seaburg chipset) systems with total of 32 Harpertown ...
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DMI 1.0, introduced in 2004 with a data transfer rate of 1 GB/s with a ×4 link. DMI 2.0 , introduced in 2011, doubles the data transfer rate to 2 GB/s with a ×4 link. It is used to link an Intel CPU with the Intel Platform Controller Hub (PCH), which supersedes the historic implementation of a separate northbridge and southbridge.