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DRAM memory may provide increased protection against soft errors by relying on error-correcting codes. Such error-correcting memory, known as ECC or EDAC-protected memory, is particularly desirable for highly fault-tolerant applications, such as servers, as well as deep-space applications due to increased radiation.
Low-density parity-check (LDPC) codes are a class of highly efficient linear block codes made from many single parity check (SPC) codes. They can provide performance very close to the channel capacity (the theoretical maximum) using an iterated soft-decision decoding approach, at linear time complexity in terms of their block length.
This is the case in computer memory (usually RAM), where bit errors are extremely rare and Hamming codes are widely used, and a RAM with this correction system is an ECC RAM . In this context, an extended Hamming code having one extra parity bit is often used.
Error-correcting codes are used in lower-layer communication such as cellular network, high-speed fiber-optic communication and Wi-Fi, [11] [12] as well as for reliable storage in media such as flash memory, hard disk and RAM. [13] Error-correcting codes are usually distinguished between convolutional codes and block codes:
Since then errors have become less visible as simple parity RAM has fallen out of use; either they are invisible as they are not detected, or they are corrected invisibly with ECC RAM. Modern RAM is believed, with much justification, to be reliable, and error-detecting RAM has largely fallen out of use for non-critical applications.
Memory scrubbing consists of reading from each computer memory location, correcting bit errors (if any) with an error-correcting code , and writing the corrected data back to the same location. [ 1 ] Due to the high integration density of modern computer memory chips , the individual memory cell structures became small enough to be vulnerable ...
Chipkill is frequently combined with dynamic bit-steering, so that if a chip fails (or has exceeded a threshold of bit errors), another, spare, memory chip is used to replace the failed chip. The concept is similar to that of RAID , which protects against disk failure, except that now the concept is applied to individual memory chips.
Unlike DDR4, all DDR5 chips have on-die error-correction code, that detects and corrects errors before sending data to the CPU, to improve reliability and allow denser RAM chips which lowers per-chip defect rate. However, on-die error-correction code is not the same as true ECC memory with extra data correction chips on the memory module. There ...