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The AMD Jaguar Family 16h is a low-power microarchitecture designed by AMD. It is used in APUs succeeding the Bobcat Family microarchitecture in 2013 and being succeeded by AMD's Puma architecture in 2014. It is two-way superscalar and capable of out-of-order execution.
AMD Family 10h (K10) – based on the K8 microarchitecture. Shared Level 3 Cache, 128-bit floating point units, AMD-V Nested Paging virtualization, and HyperTransport 3.0 are introduced. Barcelona was the first design which implemented it. AMD Family 11h – combined elements of K8 and K10 designs for Turion X2 Ultra / Puma mobile platform.
The Puma cores use the same microarchitecture as Jaguar, and inherits the design: Out-of-order execution and Speculative execution, up to 4 CPU cores; Two-way integer execution; Two-way 128-bit wide floating-point and packed integer execution; Integer hardware divider; Puma does not feature clustered multi-thread (CMT), meaning that there are ...
Microarchitecture Year Pipeline stages Misc Elbrus-8S: 2014 VLIW, Elbrus (proprietary, closed) version 5, 64-bit AMD K5: 1996 5 Superscalar, branch prediction, speculative execution, out-of-order execution, register renaming [a] AMD K6: 1997 6 Superscalar, branch prediction, speculative execution, out-of-order execution, register renaming [b ...
In the fall of 2008, Cray delivered the Jaguar 1.3 petaflops XT5 system to National Center for Computational Sciences at Oak Ridge National Laboratory. The system, with over 150,000 processing cores, was the second fastest system in the world for the LINPACK benchmark, [ 2 ] the fastest system available for open science and the first system to ...
reengineered P6-based microarchitecture used in Intel Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion and enhanced micro-op fusion with a wider front end and decoder, larger out-of-order core and renamed register, support loop stream detector and large shadow register file.
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The AMD Bobcat Family 14h is a microarchitecture created by AMD for its AMD APUs, aimed at a low-power/low-cost market. [ 1 ] It was revealed during a speech from AMD executive vice-president Henri Richard in Computex 2007 and was put into production Q1 2011. [ 2 ]