Search results
Results from the WOW.Com Content Network
Because the CAS latency is specified in clock cycles, and not transfers (which occur on both the rising and falling edges of the clock), it is important to ensure it is the clock rate (half of the transfer rate) which is being used to compute CAS latency times. [citation needed] Another complicating factor is the use of burst transfers.
Definition CAS latency: CL: The number of cycles between sending a column address to the memory and the beginning of the data in response. This is the number of cycles it takes to read the first bit of memory from a DRAM with the correct row already open.
In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller. Any value may be programmed, but the SDRAM will not operate correctly if it is too low.
In FPM DRAM, the column address can be supplied while CAS is still deasserted, and the main column access time (t AA) begins as soon as the address is stable. The CAS signal is only needed to enable the output (the data out pins were held at high-Z while CAS was deasserted), so time from CAS assertion to data valid (t CAC) is greatly reduced. [63]
The highest-rated DDR2 modules in 2009 operate at 533 MHz (1066 MT/s), compared to the highest-rated DDR modules operating at 200 MHz (400 MT/s). At the same time, the CAS latency of 11.2 ns = 6 / (bus clock rate) for the best PC2-8500 modules is comparable to that of 10 ns = 4 / (bus clock rate) for the best PC-3200 modules.
AOL Mail welcomes Verizon customers to our safe and delightful email experience!
CAS latency (CL) Clock cycles between sending a column address to the memory and the beginning of the data in response tRCD Clock cycles between row activate and ...
If you love Scrabble, you'll love the wonderful word game fun of Just Words. Play Just Words free online!