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2. PCI Express - Wikipedia

   en.wikipedia.org/wiki/PCI_Express

   On 29 November 2011, PCI-SIG preliminarily announced PCI Express 4.0, [71] providing a 16 GT/s bit rate that doubles the bandwidth provided by PCI Express 3.0 to 31.5 GB/s in each direction for a 16-lane configuration, while maintaining backward and forward compatibility in both software support and used mechanical interface. [72]

3. PCI-X - Wikipedia

   en.wikipedia.org/wiki/PCI-X

   The PCI-X standard was developed jointly by IBM, HP, and Compaq and submitted for approval in 1998. It was an effort to codify proprietary server extensions to the PCI local bus to address several shortcomings in PCI, and increase performance of high bandwidth devices, such as Gigabit Ethernet, Fibre Channel, and Ultra3 SCSI cards, and allow processors to be interconnected in clusters.

4. List of interface bit rates - Wikipedia

   en.wikipedia.org/wiki/List_of_interface_bit_rates

   1.212 GB/s: 2013 External PCI Express 2.0 ×4: 16 Gbit/s: 2 GB/s: Thunderbolt: 2 × 10 Gbit/s: 2 × 1.25 GB/s: 2011 USB 3.2 SuperSpeed+ (aka USB 3.2 Gen 2×2 USB4 Gen 2×2, USB4 Gen 3×1) [45] 20 Gbit/s: 2.424 GB/s: 2017 Thunderbolt 2: 20 Gbit/s: 2.5 GB/s: 2013 FPGA Mezzanine Card Plus (FMC+) [46] 28 Gbit/s: 3.5 GB/s: 2019 External PCI Express ...

5. List of Intel Xeon chipsets - Wikipedia

   en.wikipedia.org/wiki/List_of_Intel_Xeon_chipsets

   PCI Express 2.0 ×4 + PCI Express 1.0 4 × 1 ports, DMI for processor 6 × USB 2.0, 2 × SATA 1.5/3 Gbit/s, 4 × Integrated LAN, 20 Gbit/s QuickAssist Ivy Bridge -based Xeon chipsets

6. Peripheral Component Interconnect - Wikipedia

   en.wikipedia.org/wiki/Peripheral_Component...

   A typical 32-bit, 5 V-only PCI card, in this case, a SCSI adapter from Adaptec A motherboard with two 32-bit PCI slots and two sizes of PCI Express slots. Work on PCI began at the Intel Architecture Labs (IAL, also Architecture Development Lab) c. 1990. A team of primarily IAL engineers defined the architecture and developed a proof of concept ...

7. I/O Controller Hub - Wikipedia

   en.wikipedia.org/wiki/I/O_Controller_Hub

   ICH6 was Intel's first PCI Express southbridge, to pair with the i910 and i915 MCH. It made four PCI Express ×1 ports available. Faster ×16-Ports were accommodated in the MCH. The bottleneck Hub interface was replaced by a new Direct Media Interface (in reality a PCI Express ×4 link) with 1 GB/s of bandwidth per direction