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Processor clock speeds increased by more than tenfold between 1990 and 1999, and 64-bit processors began to emerge later in the decade. In the 1990s, microprocessors no longer used the same clock speed for the processor and the RAM. Processors began to have a front-side bus (FSB) clock speed used in communication with RAM and other components ...
CPUID code {{{cpuid}}} Product code {{{code}}} Max. CPU clock rate {{{slowest}}} {{{slow-unit}}} to {{{fastest}}} {{{fast-unit}}} FSB speeds {{{fsb-slowest}}} {{{fsb ...
This is a documentation subpage for Template:Infobox CPU. It may contain usage information, categories and other content that is not part of the original template page. This template uses Lua :
is the desktop/laptop processor codename ("x86 TICK") is a spacer column; is the (single-core) NetBurst processor name. It is reserved to insert the NetBurst microarchitecture only, and is used solely to add NetBurst development in parallel with P6 development. Columns 9–13 are not anticipated to require any further updating unless Intel adds ...
is the (hyperthreading) NetBurst processor name. is a spacer column with arrows to show the derivation of hyperthreading NetBurst processors; is the (dual-core) NetBurst processor name. Because the dual-core NetBurst processor physically consisted of two dies on the same package, the graphical illustration displays this as a horizontal evolution.
The following is a partial list of Intel CPU microarchitectures. The list is incomplete, additional details can be found in Intel's tick–tock model, process–architecture–optimization model and Template:Intel processor roadmap.
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Pentium Pro with MMX and improved 16-bit performance; 242-pin Slot 1 (SEC) processor package; Voltage identification pins; 7.5 million transistors; 32 KB L1 cache; 512 KB 1 ⁄ 2 frequency external L2 cache; The Performance Enhanced mobile Pentium II (codenamed Dixon) had a full-speed 256 KB L2 cache; Klamath – 0.35 μm process technology ...