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Column address strobe latency, also called CAS latency or CL, is the delay in clock cycles between the READ command and the moment data is available. [ 1 ] [ 2 ] In asynchronous DRAM , the interval is specified in nanoseconds (absolute time). [ 3 ]
CAS, the Column Address Strobe. The address inputs are captured on the falling edge of CAS, and select a column from the currently open row to read or write. WE, Write Enable. This signal determines whether a given falling edge of CAS is a read (if high) or write (if low). If low, the data inputs are also captured on the falling edge of CAS.
Some CAS-based algorithms are affected by and must handle the problem of a false positive match, or the ABA problem. It is possible that between the time the old value is read and the time CAS is attempted, some other processors or threads change the memory location two or more times such that it acquires a bit pattern which matches the old value.
With this 1 ns clock, a CAS latency of 7 gives an absolute CAS latency of 7 ns. Faster DDR3-2666 memory (with a 1333 MHz clock, or 0.75 ns exactly; the 1333 is rounded) may have a larger CAS latency of 9, but at a clock frequency of 1333 MHz the amount of time to wait 9 clock cycles is only 6.75 ns.
Although more confusing to humans, this can be easier to implement in hardware, and is preferred by Intel for its microprocessors. [citation needed] If the requested column address is at the start of a block, both burst modes (sequential and interleaved) return data in the same sequential sequence 0-1-2-3-4-5-6-7.
One more column address bit (C10) is added, allowing up to 8192 columns (1 KB pages) in ×4 chips (11 → 12). The least-significant three column-address bits (C0, C1, C2) are removed. All reads and writes must begin at a column address which is a multiple of 8 (3 → 0). This is necessary due to the internal ECC.
More recently, however, it has been shown that an STM can be implemented with comparable properties [clarification needed] using only CAS. [3] An lock-free deque using hazard pointers and requiring only DWCAS rather than full DCAS was proposed by Maged Michael in 2003. [4]
The results may be a list of the identical content in multiple locations. In a CAS, more than one document may be returned for a given search, but each of those documents will be unique and presented only once. Another advantage to CAS is that the physical location in storage is not part of the lookup system.