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An open collector output processes an IC's output through the base of an internal bipolar junction transistor (BJT), whose collector is exposed as the external output pin. For NPN open collector outputs, the emitter of the NPN transistor is internally connected to ground, [1] so the NPN open collector internally forms either a short-circuit ...
The common collector amplifier's low output impedance allows a source with a large output impedance to drive a small load impedance without changing its voltage. Thus this circuit finds applications as a voltage buffer. In other words, the circuit has current gain (which depends largely on the h FE of the transistor) instead of voltage gain. A ...
The OSSD outputs are self-checked. In the non-tripped state, the outputs periodically pulse low. The protective device checks the output, to make sure it does indeed go low when commanded. If not, the output may have failed or has shorted to 24V somewhere else.
Top: NPN base width for low collector–base reverse bias; Bottom: narrower NPN base width for large collector–base reverse bias. Hashed regions are depleted regions. As the collector–base voltage (=) varies, the collector–base depletion region varies in size. An increase in the collector–base voltage, for example, causes a greater ...
NPN based circuits used +6V and -6V and the transistor switched at close to -6V, PNP based circuits used 0V and -12V and the transistor switched at close to 0V. Thus for example a NPN gate driven by a PNP gate would see the threshold voltage of -6V in the middle of the range of 0V to -12V.
Efficiency is mediocre because single npn-type transistors or Darlington pairs require fairly a high collector-emitter voltage drop. [28] A single common-emitter pnp-type transistor can operate correctly in saturation mode, with only ≈0.25 V voltage drop, but also with impractically high base currents. [29]
An IGBT cell is constructed similarly to an n-channel vertical-construction power MOSFET, except the n+ drain is replaced with a p+ collector layer, thus forming a vertical PNP bipolar junction transistor. This additional p+ region creates a cascade connection of a PNP bipolar junction transistor with the surface n-channel MOSFET. The whole ...
"The disadvantages are that more different power supply voltages are needed, and both pnp and npn transistors are required." [9] Instead of alternating NPN and PNP stages, another coupling method employed Zener diodes and resistors to shift the output logic levels to be the same as the input logic levels. [17]