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To mask an interrupt is to disable it, so it is deferred [b] or ignored [c] by the processor, while to unmask an interrupt is to enable it. [9] Processors typically have an internal interrupt mask register, [d] which allows selective enabling [2] (and disabling) of hardware interrupts. Each interrupt signal is associated with a bit in the mask ...
The detection of a RESET signal causes the processor to enter a system initialization period of six clock cycles, after which it sets the interrupt request disable flag in the status register and loads the program counter with the values stored at the processor initialization vector ($00FFFC – $00FFFD) before commencing execution. [1]
The Interrupt flag (IF) is a flag bit in the CPU's FLAGS register, which determines whether or not the (CPU) will respond immediately to maskable hardware interrupts. [1] If the flag is set to 1 maskable interrupts are enabled. If reset (set to 0) such interrupts will be disabled until
Clock-comparator subclass mask 0 21 CPU-timer subclass mask 0 22 Service-signal subclass mask 0 24 Set to 1 0 25 Interrupt-key subclass mask 0 26 Set to 1 0 27 ETR subclass mask 0 28 Program-call-fast 0 29 Crypto control 1 0 Primary space-switch-event control 1 1-19 Primary segment-table origin 1 22 Primary subspace-group control 1 23
FLAGS registers can be moved from or to the stack. This is part of the job of saving and restoring CPU context, against a routine such as an interrupt service routine whose changes to registers should not be seen by the calling code. Here are the relevant instructions: The PUSHF and POPF instructions transfer the 16-bit FLAGS register.
With regard to SPARC, the non-maskable interrupt (NMI), despite having the highest priority among interrupts, can be prevented from occurring through the use of an interrupt mask. [1] An NMI is often used when response time is critical or when an interrupt should never be disabled during normal system operation.
The IRR specifies which interrupts are pending acknowledgement, and is typically a symbolic register which can not be directly accessed. The ISR register specifies which interrupts have been acknowledged, but are still waiting for an end of interrupt (EOI). The IMR specifies which interrupts are to be ignored and not acknowledged.
Processor exceptions generated by the CPU have fixed mapping to the first up to 32 interrupt vectors. [1] While 32 vectors (0x00-0x1f) are officially reserved (and many of them are used in newer processors), the original 8086 used only the first five (0-4) interrupt vectors and the IBM PC IDT layout did not respect the reserved range.