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IRQ 1 – keyboard on PS/2 port (cannot be changed) IRQ 2 – 8259 interrupt controller; cascaded signals from IRQs 8–15; IRQ 3 – serial port controller for serial port 2 (shared with serial port 4, if present) IRQ 4 – serial port controller for serial port 1 (shared with serial port 3, if present) IRQ 5 – parallel port 3 or ISA sound card
Logical parallel port 3: I/O port 0x278, IRQ 5 (dedicated IO cards or using a controller built into the mainboard) If no printer port is present at 0x3BC, the second port in the row (0x378) becomes logical parallel port 1 and 0x278 becomes logical parallel port 2 for the BIOS.
* Parallel 2: IRQ 5/7 (There is no technical reason why 3,4,5,7,9 cannot all be selectable choices for each port.) Also, although some later ISA devices were capable of automatic configuration, it was common for PC ISA expansion cards to limit themselves to a very small number of choices for interrupt request lines.
Closeup of an Intel 8259A IRQ chip from a PC XT. Pinout. The Intel 8259 is a programmable interrupt controller (PIC) designed for the Intel 8085 and 8086 microprocessors. The initial part was 8259, a later A suffix version was upward compatible and usable with the 8086 or 8088 processor.
The sequence (according to chapter 14 of The Undocumented PC by Frank Van Gilluwe) is 3BC,378 and finally 278. The 3BC address was used by the parallel port found on the MDA video card while the 378 & 278 were originally found on ISA parallel port cards and later integrated into motherboard chipsets. I will update the table to reflect this.
[nb 4] Hence the interrupt service routine must retrieve a copy of the saved status register from where it was pushed onto the stack and check the status of the B flag in order to distinguish between an IRQ and a BRK. [1] [2] [4] This requirement is eliminated when operating the 65C802/65C816 in native mode, due to the separate vectors for the ...
A hardware interrupt is a condition related to the state of the hardware that may be signaled by an external hardware device, e.g., an interrupt request (IRQ) line on a PC, or detected by devices embedded in processor logic (e.g., the CPU timer in IBM System/370), to communicate that the device needs attention from the operating system (OS) [7] or, if there is no OS, from the bare metal ...
The interrupt priority level (IPL) is a part of the current system interrupt state, which indicates the interrupt requests that will currently be accepted. The IPL may be indicated in hardware by the registers in a programmable interrupt controller, or in software by a bitmask or integer value and source code of threads.