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  2. List of AMD chipsets - Wikipedia

    en.wikipedia.org/wiki/List_of_AMD_chipsets

    OR single PCI-E 2.0 x16 Mobile Chipset, Tigris platform AMD 880M chipset Athlon II Neo, Turion II Neo Radeon HD 4225 No DirectX 10.1, UVD2, HDMI/HDCP, DisplayPort, DVI, VGA, OR Single PCI-E 2.0 x16 Mobile Chipset, Nile platform AMD 880M chipset Mobile Phenom II, Mobile Turion II, Mobile Athlon II, Mobile Sempron V-Series Radeon HD 4250 Radeon ...

  3. Template:AM4 chipsets - Wikipedia

    en.wikipedia.org/wiki/Template:AM4_chipsets

    Processor overclocking TDP ... PCIe 2.0 ×4 No No 1, 2, 6 4 0, 1, 10 No Limited [e] ~5.8 W [10] Yes ... B550 [h] Jun 2020 [14] [15] PCIe 3.0 ×10 Yes

  4. Table of AMD processors - Wikipedia

    en.wikipedia.org/wiki/Table_of_AMD_processors

    Bus Speed & Type [a] Cache Socket Memory Controller Features L1 L2 L3 SIMD Speed/Power Other Changes Am386 Am386: Sx/SxL/SxLV [1] 1 No 25–40 [1] FSB 100 PQFP [1] discrete: Am486 [2] 500, 350 Am486: 1 No 25–120 FSB 8 168 pin PGA 208 SQFP discrete: 500, 350 Enhanced Am486: 66–120 FSB 8, 8/16 168 pin PGA 208 SQFP [3] Am5x86 350 Am5x86: X5 ...

  5. Socket AM4 - Wikipedia

    en.wikipedia.org/wiki/Socket_AM4

    PCIe 2.0 ×4 No No 1, 2, 6 4 0, 1, 10 No ... B550 [h] Jun 2020 [35] [36] PCIe 3.0 ×10 ... This would be achieved by disabling support for some older AM4 processors ...

  6. List of AMD Athlon processors - Wikipedia

    en.wikipedia.org/wiki/List_of_AMD_Athlon_processors

    CPU GPU Socket PCIe lanes Memory support TDP Part Number Cores Clock rate Cache [a] Model Config [b] Clock Processing power [c] Base Boost L1 L2 L3; Athlon Pro 300GE [20] Sept. 30 2019 OEM 14 nm (Dali) 2 (4) 3.4 — 64 KB inst. 32 KB data per core 512 KB per core 4 MB Vega 3 192:12:4 3 CU 1100 MHz 424.4 AM4 16 (8+4+4) DDR4-2667 dual-channel: 35 W

  7. Template:AMD Ryzen 5000 Series - Wikipedia

    en.wikipedia.org/wiki/Template:AMD_Ryzen_5000_Series

    Socket: AM4. All the CPUs support DDR4-3200 in dual-channel mode. All the CPUs support 24 PCIe 4.0 lanes. 4 of the lanes are reserved as link to the chipset. No integrated graphics. L1 cache: 64 KB per core (32 KB data + 32 KB instruction). L2 cache: 512 KB per core. Fabrication process: TSMC 7FF.

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