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Specific Northbridge IC must be used for PowerPC CPU. It is impossible to use Northbridge for Intel or AMD x86 CPU with PowerPC CPU. However it is possible to use certain types of x86 Southbridge in PowerPC based motherboards. Example: VIA 686B and AMD Geode CS5536. Apple UniNorth 2 AGP used in PowerPC 74xx Based Macs
A common example of a northbridge on a PowerPC platform is in Apple's older PowerPC-based computers like the iMac G5, which utilized an IBM CPC945 Northbridge chip. According to an Apple Developer note, The Power Mac G5's northbridge chip connected to a "Mid Bridge", which then connected to a south bridge. [9]
Common Hardware Reference Platform (CHRP) is a standard system architecture for PowerPC-based computer systems published jointly by IBM and Apple in 1995. Like its predecessor PReP, it was conceptualized as a design to allow various operating systems to run on an industry standard hardware platform, and specified the use of Open Firmware and RTAS for machine abstraction purposes.
An operating system running on PowerPC 615 could either choose to execute 32-bit or 64-bit PowerPC instructions, 32-bit x86 instructions or a mix of three. Mixing instructions would involve a context switch in the CPU with a small overhead. The only operating systems that supported the 615 were Minix and a special development version of OS/2. [38]
The PowerPC 740 and 750 (codename Arthur) [2] were introduced in late 1997 as an evolutionary replacement for the PowerPC 603e. Enhancements included a faster 60x system bus (66 MHz), larger L1 caches (32 KB instruction and 32 KB data), a second integer unit, an enhanced floating point unit, and higher core frequency. The 750 had support for an ...
The RS/6000 CPU had 2 configurations, called the "RIOS-1" and "RIOS.9" (or more commonly the "POWER1" CPU). A RIOS-1 configuration had a total of 10 discrete chips - an instruction cache chip, fixed-point chip, floating-point chip, 4 data cache chips, storage control chip, input/output chips, and a clock chip.
The PowerPC e500 is a 32-bit microprocessor core from Freescale Semiconductor. The core is compatible with the older PowerPC Book E specification as well as the Power ISA v.2.03 . [ citation needed ] It has a dual issue, seven-stage pipeline with FPUs (from version 2 onwards), 32/32 KiB data and instruction L1 caches and 256, 512 or 1024 KiB L2 ...
The PowerPC 400 family is a line of 32-bit embedded RISC processor cores based on the PowerPC or Power ISA instruction set architectures.The cores are designed to fit inside specialized applications ranging from system-on-a-chip (SoC) microcontrollers, network appliances, application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) to set-top boxes, storage ...