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  2. Serial Peripheral Interface - Wikipedia

    en.wikipedia.org/wiki/Serial_Peripheral_Interface

    A Queued Serial Peripheral Interface (QSPI; different to but has same abbreviation as Quad SPI described in § Quad SPI) is a type of SPI controller that uses a data queue to transfer data across an SPI bus. [19] It has a wrap-around mode allowing continuous transfers to and from the queue with only intermittent attention from the CPU.

  3. System Packet Interface - Wikipedia

    en.wikipedia.org/wiki/System_Packet_Interface

    The SPI 4.2 interface is composed of high speed clock, control, and data lines and lower speed FIFO buffer status lines. The high speed data line include a 16-bit data bus, a 1 bit control line and a double data rate (DDR) clock. The clock can run up to 500 MHz, supporting up to 1 GigaTransfer per second.

  4. Peripheral Sensor Interface 5 - Wikipedia

    en.wikipedia.org/wiki/Peripheral_Sensor_Interface_5

    Peripheral Sensor Interface (PSI5) is a digital interface for sensors. PSI5 is a two-wire interface, used to connect peripheral sensors to electronic control units in automotive electronics . Both point-to-point and bus configurations with asynchronous and synchronous data transmission are supported.

  5. Low Pin Count - Wikipedia

    en.wikipedia.org/wiki/Low_Pin_Count

    Low Pin Count interface Winbond chip Trusted Platform Module installed on a motherboard, and using the LPC bus. The Low Pin Count (LPC) bus is a computer bus used on IBM-compatible personal computers to connect low-bandwidth devices to the CPU, such as the BIOS ROM (BIOS ROM was moved to the Serial Peripheral Interface (SPI) bus in 2006 [1]), "legacy" I/O devices (integrated into Super I/O ...

  6. SPI-4.2 - Wikipedia

    en.wikipedia.org/wiki/SPI-4.2

    SPI-4.2 is a version of the System Packet Interface published by the Optical Internetworking Forum. It was designed to be used in systems that support OC-192 SONET interfaces and is sometimes used in 10 Gigabit Ethernet based systems.

  7. I3C (bus) - Wikipedia

    en.wikipedia.org/wiki/I3C_(bus)

    Goals of the MIPI Sensor Working Group effort were first announced in November 2014 at the MEMS Executive Congress in Scottsdale AZ. [8]Electronic design automation tool vendors including Cadence, [9] Synopsys [10] and Silvaco [11] have released controller IP blocks and associated verification software for the implementation of the I3C bus in new integrated circuit designs.

  8. Simple Sensor Interface protocol - Wikipedia

    en.wikipedia.org/wiki/Simple_Sensor_Interface...

    The Simple Sensor Interface (SSI) protocol is a simple communications protocol designed for data transfer between computers or user terminals and smart sensors. The SSI protocol has been developed jointly by Nokia , Vaisala , Suunto , Ionific, Mermit and University of Oulu .

  9. Camera Serial Interface - Wikipedia

    en.wikipedia.org/wiki/Camera_Serial_Interface

    MIPI CSI-3 is a high-speed, bidirectional protocol primarily intended for image and video transmission between cameras and hosts within a multi-layered, peer-to-peer, UniPro-based M-PHY device network. It was originally released in 2012 and got re-released in version 1.1 in 2014. [7]