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High-level synthesis ( HLS ), sometimes referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that takes an abstract behavioral specification of a digital system and finds a register-transfer level structure that realizes the given behavior. [ 1][ 2][ 3]
A high-level design provides an overview of a system, product, service, or process. Such an overview helps supporting components be compatible to others. The highest-level design should briefly describe all platforms, systems, products, services, and processes that it depends on, and include any important changes that need to be made to them.
Example of a high-level systems architecture for a computer. A system architecture is the conceptual model that defines the structure, behavior, and more views of a system. An architecture description is a formal description and representation of a system, organized in a way that supports reasoning about the structures and behaviors of the system.
High-level describe those operations that are more abstract and general in nature; wherein the overall goals and systemic features are typically more concerned with the wider, macro system as a whole. Low-level describes more specific individual components of a systematic operation, focusing on the details of rudimentary micro functions rather ...
Software design usually is directed by goals for the resulting system and involves problem-solving and planning – including both high-level software architecture and low-level component and algorithm design. In terms of the waterfall development process, software design is the activity of following requirements specification and before coding ...
A systems development life cycle is composed of distinct work phases that are used by systems engineers and systems developers to deliver information systems.Like anything that is manufactured on an assembly line, an SDLC aims to produce high-quality systems that meet or exceed expectations, based on requirements, by delivering systems within scheduled time frames and cost estimates. [3]
Electronic system level (ESL) design and verification is an electronic design methodology, focused on higher abstraction level concerns. The term Electronic System Level or ESL Design was first defined by Gartner Dataquest, an EDA-industry-analysis firm, on February 1, 2001. [1] It is defined in ESL Design and Verification [2] as: "the ...
High-level verification ( HLV ), or electronic system-level ( ESL) verification, is the task to verify ESL designs at high abstraction level, i.e., it is the task to verify a model that represents hardware above register-transfer level (RTL) abstract level. For high-level synthesis (HLS or C synthesis), HLV is to HLS as functional verification ...
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