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  2. PCI configuration space - Wikipedia

    en.wikipedia.org/wiki/PCI_configuration_space

    One of the major improvements the PCI Local Bus had over other I/O architectures was its configuration mechanism. In addition to the normal memory-mapped and I/O port spaces, each device function on the bus has a configuration space, which is 256 bytes long, addressable by knowing the eight-bit PCI bus, five-bit device, and three-bit function numbers for the device (commonly referred to as the ...

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  4. System Management Bus - Wikipedia

    en.wikipedia.org/wiki/System_Management_Bus

    SMBus defines a clock low time-out, TIMEOUT of 35 ms. I²C does not specify any timeout limit. SMBus specifies T LOW:SEXT as the cumulative clock low extend time for a slave device. I²C does not have a similar specification. SMBus specifies T LOW:MEXT as the cumulative clock low extend time for a master device. Again I²C does not have a ...

  5. Key Code Qualifier - Wikipedia

    en.wikipedia.org/wiki/Key_Code_Qualifier

    Key Code Qualifier is an error-code returned by a SCSI device. When a SCSI target device returns a check condition in response to a command, the initiator usually then issues a SCSI Request Sense command. This process is part of a SCSI protocol called Contingent Allegiance Condition.

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  7. Option ROM - Wikipedia

    en.wikipedia.org/wiki/Option_ROM

    If a device has no PnP Expansion header, it may perform any hook in the routine at +03h, as it is a legacy card. In the initial initialization routine, as the Option ROM points to a PCI data structure (not the same as the configuration space), the option ROM code knows the device and vendor ID is at a fixed offset from RIP.

  8. POST card - Wikipedia

    en.wikipedia.org/wiki/POST_card

    POST cards are inserted into an expansion slot, and are available with connectors for the ISA (also supporting EISA), PCI, PCI Express, Mini PCIe (for laptops), Universal Serial Bus, or Low Pin Count bus, or for a parallel port. A typical card for desktop computers has a different bus interface on each edge; a card for laptop computers may have ...

  9. Peripheral Component Interconnect - Wikipedia

    en.wikipedia.org/wiki/Peripheral_Component...

    Generally, PCI writes are faster than PCI reads, because a device may buffer the incoming write data and release the bus faster. For a read, it must delay the data phase until the data has been fetched. 100x: Reserved A PCI device must not respond to an address cycle with these command codes. 1010: Configuration Read