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This article lists x86-compliant microprocessors sold by VIA Technologies, grouped by technical merits: cores within same group have much in common. Cyrix design ( Cyrix III ) [ edit ]
VIA chipsets support CPUs from Intel, AMD (e.g. the Athlon 64) and VIA themselves (e.g. the VIA C3 or C7).They support CPUs as old as the i386 in the early 1990s. In the early 2000s, their chipsets began to offer on-chip graphics support from VIA's joint venture with S3 Graphics beginning in 2001; this support continued into the early 2010s, with the release of the VX11H in August 2012.
That same year, VIA acquired Centaur Technology from Integrated Device Technology, marking its entry into the x86 microprocessor market. VIA is the maker of the VIA C3, VIA C7 & VIA Nano processors, and the EPIA platform. The Cyrix MediaGX platform remained with National Semiconductor. In 2001, VIA established the S3 Graphics joint venture.
This category contains articles about x86-compatible microprocessors by VIA Technologies. Pages in category "VIA Technologies x86 microprocessors" The following 15 pages are in this category, out of 15 total.
VIA PadLock is a central processing unit (CPU) instruction set extension to the x86 microprocessor instruction set architecture (ISA) found on processors produced by VIA Technologies and Zhaoxin. Introduced in 2003 with the VIA Centaur CPUs, the additional instructions provide hardware-accelerated random number generation (RNG), Advanced ...
Instruction set extensions that have been added to the x86 instruction set in order to support hardware virtualization.These extensions provide instructions for entering and leaving a virtualized execution context and for loading virtual-machine control structures (VMCSs), which hold the state of the guest and host, along with fields which control processor behavior within the virtual machine.
The chips would have a 100 and 133 MHz FSB, 128 KB of L1 cache along with MMX and 3DNow instructions. The chips would be produced using a 0.15 micron process and have a die size of 52 square mm. VIA planned to release a later version of the chip, code-named Ezra/C5C with a 0.13 micron process and speeds of 750 MHz up to possibly 1 GHz. [5]
In 2018 researcher Christopher Domas reported that the prefix 0x620405 (x86 BOUND) also worked. A proposal made in 2002 to add AIS support to the Netwide Assembler (NASM) was partially declined in 2005, on the basis that NASM was an x86 assembler, and AIS is a separate instruction set. [4] An assembler is available from Domas's 2018 research. [5]