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The first Verilog simulator available on the Windows OS. The simulator had a cycle-based counterpart called 'CycleDrive'. FrontLine was sold to Avant! in 1998, which was later acquired by Synopsys in 2002. Synopsys discontinued Purespeed in favor of its well-established VCS simulator. Quartus II Simulator (Qsim) Altera: VHDL-1993, V2001, SV2005
Synopsys, Inc. is an American electronic design automation (EDA) company headquartered in Sunnyvale, California, that focuses on silicon design and verification, silicon intellectual property and software security and quality. Synopsys supplies tools and services to the semiconductor design and manufacturing industry.
The world of electronic design automation (EDA) software for integrated circuit (IC) design is dominated by the three vendors Synopsys, Cadence Design Systems and Siemens EDA (Formerly Mentor Graphics, acquired in 2017 by Siemens) which have a revenue respectively of 4,2 billion US$, 3 billion US$ and 1,3 billion US$.
The first distributed VCS, demoed in 1997, [69] released soon after. CVS: First publicly released July 3, 1986; based on RCS: NetBSD, OpenBSD: CVSNT: First publicly released 1998; based on CVS. Started by CVS developers with the goal adding support for a wider range of development methods and processes. darcs: First announced on April 9, 2003 ...
Synopsys on Wednesday showed a set of software tools designed to make it easier and faster to design cars, data centers and other big systems that rely on semiconductors. Synopsys is one of the ...
In the design verification role, SystemVerilog is widely used in the chip-design industry. The three largest EDA vendors (Cadence Design Systems, Mentor Graphics, Synopsys) have incorporated SystemVerilog into their mixed-language HDL simulators.
Having worked on the GUI used by Synopsys, I can understand how they were able to integrate SystemVerilog quite quickly. The VCS GUI was developed independently of the simulator, (by Simulation Technologies, later Summit Design )and was designed to be able to work with different simulators and different HD Languages (concurrently, no less).
In semiconductor design, standard-cell methodology is a method of designing application-specific integrated circuits (ASICs) with mostly digital-logic features. Standard-cell methodology is an example of design abstraction, whereby a low-level very-large-scale integration layout is encapsulated into an abstract logic representation (such as a NAND gate).