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For an NPN open emitter output, the collector is connected to the positive voltage rail, so the emitter outputs a high voltage when the transistor is on and is hi-Z when off. For a PNP open emitter output, the collector is connected to the low voltage supply, so the emitter outputs a low voltage when the transistor is on and is hi-Z when off.
See also: Diode logic § Active-high AND logic gate Open-collector buffers connected as wired AND.. The wired AND connection is a form of AND gate.When using open collector or similar outputs (which can be identified by the ⎐ symbol in schematics), wired AND only requires a pull up resistor on the shared output wire.
A common variation omits the collector resistor of the output transistor, making an open-collector output. This allows the designer to fabricate wired logic by connecting the open-collector outputs of several logic gates together and providing a single external pull-up resistor. If any of the logic gates becomes logic low (transistor conducting ...
open-collector 30 V / 40 mA 14 SN74LS06: 74x07 6 hex buffer gate: open-collector 30 V / 40 mA 14 SN74LS07: 74x08 4 quad 2-input AND gate: 14 SN74LS08: 74x09 4 quad 2-input AND gate open-collector 14 SN74LS09: 74x10 3 triple 3-input NAND gate 14 SN74LS10: 74x11 3 triple 3-input AND gate 14 SN74LS11: 74x12 3 triple 3-input NAND gate open ...
The basic concept of the third state, high impedance (Hi-Z), is to effectively remove the device's influence from the rest of the circuit. If more than one device is electrically connected to another device, putting an output into the Hi-Z state is often used to prevent short circuits, or one device driving high (logical 1) against another device driving low (logical 0).
The SGPIO bus is an open collector bus with 2.0 kΩ pull-up resistors located at the HBA and the back-plane – as on any open collector bus information is transferred by devices on the bus pulling the lines to ground (GND) using an open collector transistor or open drain FET.
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A 555 timer can act as an active-low SR latch (though without an inverted Q output) with two outputs: output pin is a push-pull output, discharge pin is an open-collector output (requires a pull-up resistor). For the schematic on the right, a Reset input signal connects to the RESET pin and connecting a Set input signal to the TR pin.