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In the x86 architecture, the CPUID instruction (identified by a CPUID opcode) is a processor supplementary instruction (its name derived from CPU Identification) allowing software to discover details of the processor.
Takes as input a CPUID leaf index in EAX and, depending on leaf, a sub-index in ECX. Result is returned in EAX,EBX,ECX,EDX. [d] Instruction is serializing, and causes a mandatory #VMEXIT under virtualization. Support for CPUID can be checked by toggling bit 21 of EFLAGS (EFLAGS.ID) – if this bit can be toggled, CPUID is present. Usually 3 [e]
The instructions below are those enabled by the BMI bit in CPUID. Intel officially considers LZCNT as part of BMI, but advertises LZCNT support using the ABM CPUID feature flag. [ 3 ] BMI1 is available in AMD's Jaguar , [ 5 ] Piledriver [ 6 ] and newer processors, and in Intel's Haswell [ 7 ] and newer processors.
CPUID model numbers are 30h-3Fh. AMD Bulldozer Family 15h – the successor to 10h/K10. Bulldozer is designed for processors in the 10 to 220 W category, implementing XOP, FMA4 and CVT16 instruction sets. Orochi was the first design which implemented it. For Bulldozer, CPUID model numbers are 00h and 01h.
The AVX-512 instruction set consists of several separate sets each having their own unique CPUID feature bit. However, they are typically grouped by the processor generation that implements them. F, CD, ER, PF: introduced with Xeon Phi x200 (Knights Landing) and Xeon Gold/Platinum ( Skylake SP "Purley"), with the last two (ER and PF) being ...
The CPUID instruction can be used on both AMD and Intel CPUs to check whether the RDRAND instruction is supported. If it is, bit 30 of the ECX register is set after calling CPUID standard function 01H. [10] AMD processors are checked for the feature using the same test. [11] RDSEED availability can be checked on Intel CPUs in a similar manner.
Separate from the stack definition of a MISC architecture, is the MISC architecture being defined by the number of instructions supported. Typically a minimal instruction set computer is viewed as having 32 or fewer instructions, [1] [2] [3] where NOP, RESET, and CPUID type instructions are usually not counted by consensus due to their fundamental nature.
The update contains information about which processors it is designed for, so that this can be checked against the result of the CPUID instruction. [1] The structure is a 48-byte header, followed by 2,000 bytes intended to be read directly by the processor to be updated: [1]