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The latest badge promoting the Intel Core branding. The following is a list of Intel Core processors.This includes Intel's original Core (Solo/Duo) mobile series based on the Enhanced Pentium M microarchitecture, as well as its Core 2- (Solo/Duo/Quad/Extreme), Core i3-, Core i5-, Core i7-, Core i9-, Core M- (m3/m5/m7/m9), Core 3-, Core 5-, and Core 7- Core 9-, branded processors.
Intel Core Duo T2300 1.66 GHz; Intel Core Duo T2050 1.6 GHz; Intel Core Duo T2300e 1.66 GHz; Intel Core Duo T2080 1.73 GHz; Intel Core Duo L2500 1.83 GHz (low voltage, 15 W TDP) Intel Core Duo L2400 1.66 GHz (low voltage, 15 W TDP) Intel Core Duo L2300 1.5 GHz (low voltage, 15 W TDP) Intel Core Duo U2500 1.2 GHz (ultra-low voltage, 9 W TDP)
The most major change with Raptor Lake-S Refresh is that one fewer E-core cluster is disabled in silicon for Core i7 SKUs. CPUs in bold below feature ECC memory support only when paired with a motherboard based on the W680 chipset according to each respective Intel Ark product page.
Intel Core: Txxxx Lxxxx Uxxxx Yonah: 2006–2008 1.06 GHz – 2.33 GHz Socket M: 65 nm 5.5 W – 49 W 1 or 2 533 MHz, 667 MHz 64 KiB per core 2 MiB N/A Intel Core 2: Uxxxx Lxxxx Exxxx Txxxx P7xxx Xxxxx Qxxxx QXxxxx Allendale Conroe Merom Penryn Kentsfield Wolfdale Yorkfield: 2006–2011 1.06 GHz – 3.33 GHz Socket 775 Socket M Socket P Socket ...
Results on a 2.4 GHz Intel Core 2 Duo (1 CPU 2007) vary from 9.7 MWIPS using BASIC Interpreter, 59 MWIPS via BASIC Compiler, 347 MWIPS using 1987 Fortran, 1,534 MWIPS through HTML/Java to 2,403 MWIPS using a modern C/C++ compiler.
Successor to the Sunny Cove core, includes new security features and redesigns the cache subsystem. [17] Tiger Lake: successor to Ice Lake, using Intel's 10 nm SuperFin (10SF) process, released in Q4 2020; Golden Cove Successor to the Willow Cove core, includes improvements to performance and power efficiency. Also includes new instructions. [18]
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is the (single-core) NetBurst processor name. It is reserved to insert the NetBurst microarchitecture only, and is used solely to add NetBurst development in parallel with P6 development. Columns 9–13 are not anticipated to require any further updating unless Intel adds another parallel/stub branch of microarchitectures.
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