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Random flip-flop (RFF) is a theoretical concept of a non-sequential logic circuit capable of generating true randomness. By definition, it operates as an "ordinary" edge-triggered clocked flip-flop , except that its clock input acts randomly and with probability p = 1/2. [ 1 ]
The D flip-flop is widely used, and known as a "data" flip-flop. The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock). That captured value becomes the Q output. At other times, the output Q does not change.
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An edge-triggered RS flip flop (the combination of two clocked RS latches) is commonly used to motivate the design of the edge-triggered JK flip flop. A quick search of Google and a random click leads to which uses the edge-triggered RS flip flop as a tool to discuss the race condition that can occur (and then uses the JK flip flop as a ...
If the output of the flip-flop is low, and a high clock pulse is applied with the input being a low pulse, then there is no need for a state transition. The extra computation to sample the inputs cause an increase in setup time of the flip-flop; this is a disadvantage of this technique.
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change to nand as per comment on wikipedia page using image. i suspect whoever draw this forgot about the inverted inputs of a nand rs flip flops. 23:54, 17 June 2006 800 × 250 (30 KB)