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  2. Instruction pipelining - Wikipedia

    en.wikipedia.org/wiki/Instruction_pipelining

    In computer engineering, instruction pipelining is a technique for implementing instruction-level parallelism within a single processor. Pipelining attempts to keep every part of the processor busy with some instruction by dividing incoming instructions into a series of sequential steps (the eponymous "pipeline") performed by different processor units with different parts of instructions ...

  3. Classic RISC pipeline - Wikipedia

    en.wikipedia.org/wiki/Classic_RISC_pipeline

    The main common concept of each design is a five-stage execution instruction pipeline. During operation, each pipeline stage works on one instruction at a time. Each of these stages consists of a set of flip-flops to hold state, and combinational logic that operates on the outputs of those flip-flops.

  4. Pipeline (computing) - Wikipedia

    en.wikipedia.org/wiki/Pipeline_(computing)

    In instruction pipelines, this technique is called out-of-order execution. Guess and backtrack: One important example of item-to-item dependency is the handling of a conditional branch instruction X by an instruction pipeline. The first stage A of the pipeline, that fetches the next instruction Y to be executed, cannot perform its task until X ...

  5. Branch predictor - Wikipedia

    en.wikipedia.org/wiki/Branch_predictor

    The purpose of the branch predictor is to improve the flow in the instruction pipeline. Branch predictors play a critical role in achieving high performance in many modern pipelined microprocessor architectures. Figure 1: Example of 4-stage pipeline. The colored boxes represent instructions independent of each other.

  6. Instruction scheduling - Wikipedia

    en.wikipedia.org/wiki/Instruction_scheduling

    Local (basic block) scheduling: instructions can't move across basic block boundaries. Global scheduling : instructions can move across basic block boundaries. Modulo scheduling : an algorithm for generating software pipelining , which is a way of increasing instruction level parallelism by interleaving different iterations of an inner loop .

  7. Instruction-level parallelism - Wikipedia

    en.wikipedia.org/wiki/Instruction-level_parallelism

    Instruction-level parallelism (ILP) is the parallel or simultaneous execution of a sequence of instructions in a computer program. More specifically, ILP refers to the average number of instructions run per step of this parallel execution.

  8. Very long instruction word - Wikipedia

    en.wikipedia.org/wiki/Very_long_instruction_word

    Very long instruction word (VLIW) refers to instruction set architectures that are designed to exploit instruction-level parallelism (ILP). A VLIW processor allows programs to explicitly specify instructions to execute in parallel, whereas conventional central processing units (CPUs) mostly allow programs to specify instructions to execute in sequence only.

  9. Instruction cycle - Wikipedia

    en.wikipedia.org/wiki/Instruction_cycle

    In simpler CPUs, the instruction cycle is executed sequentially, each instruction being processed before the next one is started. In most modern CPUs, the instruction cycles are instead executed concurrently, and often in parallel, through an instruction pipeline: the next instruction starts being processed before the previous instruction has finished, which is possible because the cycle is ...