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  2. Analog delay line - Wikipedia

    en.wikipedia.org/wiki/Analog_delay_line

    The delay time of an analog delay line may be only a few nanoseconds or several milliseconds, limited by the practical size of the physical medium used to delay the signal and the propagation speed of impulses in the medium. Analog delay lines are applied in many types of signal processing circuits; for example the PAL television standard uses ...

  3. Lattice delay network - Wikipedia

    en.wikipedia.org/wiki/Lattice_delay_network

    The first example gives the circuit for a 6th order maximally flat delay. Circuit values for z a and z b for a normalized lattice (with z b the dual of z a) were given earlier. However, in this example the alternative version of z b is used, so that an unbalanced alternative can be easily produced. The circuit is

  4. Repeater insertion - Wikipedia

    en.wikipedia.org/wiki/Repeater_insertion

    An active circuit used for such a purpose is known as a repeater. In a CMOS integrated circuit, the repeater is often a simple inverter. Reducing the delay of a wire by cutting it in half and inserting a repeater is known as repeater insertion. The cost of this procedure is the additional new delay through the repeater itself, plus power cost ...

  5. Digital delay line - Wikipedia

    en.wikipedia.org/wiki/Digital_delay_line

    A digital delay line (or simply delay line, also called delay filter) is a discrete element in a digital filter, which allows a signal to be delayed by a number of samples. Delay lines are commonly used to delay audio signals feeding loudspeakers to compensate for the speed of sound in air, and to align video signals with accompanying audio ...

  6. Delay calculation - Wikipedia

    en.wikipedia.org/wiki/Delay_calculation

    Elmore delay [5] is a simple approximation, often used where speed of calculation is important but the delay through the wire itself cannot be ignored. It uses the R and C values of the wire segments in a simple calculation. The delay of each wire segment is the R of that segment times the downstream C. Then all delays are summed from the root.

  7. Quasi-delay-insensitive circuit - Wikipedia

    en.wikipedia.org/.../Quasi-delay-insensitive_circuit

    A quasi-delay-insensitive circuit (QDI circuit) is an asynchronous circuit design methodology employed in digital logic design.Developed in response to the performance challenges of building sub-micron, multi-core architectures with conventional synchronous designs, QDI circuits exhibit lower power consumption, extremely fine-grain pipelining, high circuit robustness against process–voltage ...

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  9. Bucket-brigade device - Wikipedia

    en.wikipedia.org/wiki/Bucket-brigade_device

    A well-known integrated circuit device around 1976, the Reticon SAD-1024 [2] implemented two 512-stage analog delay lines in a 16-pin DIP. It allowed clock frequencies ranging from 1.5 kHz to more than 1.5 MHz. The SAD-512 was a single delay line version.

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